ASIC Design Engineer
Cupertino, CA · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Help architect solutions for power management of the SoC - Write microarchitecture and/or design ...
New
ASIC Design Engineer
Cupertino, CA · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Help architect solutions for power management of the SoC - Write microarchitecture and/or design ...
New
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full timeposted on: Posted 22 Days Agojob requisition id: JR2020309NVIDIA is seeking ASIC Design Engineers to ...
New
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full timeposted on: Posted 22 Days Agojob requisition id: JR2020309NVIDIA is seeking ASIC Design Engineers to ...
New
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
ASIC Design Engineer
Cupertino, CA · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Help architect solutions for power management of the SoC - Write microarchitecture and/or design ...
New
ASIC Design Engineer
Cupertino, CA · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Help architect solutions for power management of the SoC - Write microarchitecture and/or design ...
New
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands‑on experience across the full ASIC development ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands‑on experience across the full ASIC development ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
Digital ASIC Design Engineer for Mixed-Signal IPs
San Diego, CA · On-site
$115.60 - $173.40/hr
Overview The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs -- including DAC, ADC, and PLLs ...
Digital ASIC Design Engineer for Mixed-Signal IPs
San Diego, CA · On-site
$115.60 - $173.40/hr
Overview The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs -- including DAC, ADC, and PLLs ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art ...
New
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art ...
New
The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for ...
The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for ...
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end--taking marketing ...
Quick apply
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end--taking marketing ...
Principal ASIC Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end-taking marketing ...
Principal ASIC Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end-taking marketing ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design with: - Architecture research and/or ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design with: - Architecture research and/or ...
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next ...
Sr. ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$160K - $225K/yr
As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design with: - Architecture research and/or ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description The ideal candidate will have experience in ASIC design with: - Architecture research and/or ...
Principal ASIC Design Engineer
Irvine, CA · On-site
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end-taking marketing ...
Principal ASIC Design Engineer
Irvine, CA · On-site
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end-taking marketing ...
ASIC Design Engineer
Irvine, CA · On-site
$108K - $172K/yr
We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...
ASIC Design Engineer
Irvine, CA · On-site
$108K - $172K/yr
We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art ...
New
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art ...
New
ASIC Design Engineer
Irvine, CA · On-site
$127.10 - $203.40/hr
We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...
ASIC Design Engineer
Irvine, CA · On-site
$127.10 - $203.40/hr
We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...
Contract Asic Design Engineer information
What is the difference between Contract Asic Design Engineer vs Contract FPGA Design Engineer?
| Aspect | Contract Asic Design Engineer | Contract FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience | Bachelor's/Master's in Electrical Engineering or Computer Engineering, FPGA/ASIC design experience |
| Work Environment | Semiconductor companies, chip design firms, contract roles in hardware development | Semiconductor companies, FPGA development firms, contract roles in hardware prototyping |
| Industry Usage | Used in chip manufacturing, integrated circuit design, hardware development | Used in prototyping, hardware acceleration, FPGA-based solutions |
The main difference between a Contract Asic Design Engineer and a Contract FPGA Design Engineer lies in their focus areas. Asic engineers work on designing custom chips for mass production, while FPGA engineers develop flexible hardware solutions using programmable logic devices. Both roles require similar educational backgrounds and often overlap in industry applications, but their end goals and tools differ.
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What are popular job titles related to Contract Asic Design Engineer jobs in California? For Contract Asic Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Contract Asic Design Engineer jobs in California look for? The top searched job categories for Contract Asic Design Engineer jobs in California are:
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Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers.
Description
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:
- Help architect solutions for power management of the SoC
- Write microarchitecture and/or design specifications for power management and other SoC level IPs
- Design, implement, and debug complex logic designs
- Integrate complex IPs into the SOC
- Support all front end integration activities like Lint, CDC, Synthesis, and ECO
- Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
- Collaborate with software and systems teams to ensure a high quality product
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Preferred Qualifications
Experience writing specifications and converting them to design.
Experience with multiple clock domains and asynchronous interfaces.
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
Ability to communicate optimally across all internal groups.
Familiarity with software and operating concepts a plus.
Familiarity with scripting languages like Perl, Python, or TCL a plus.
Description
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:
- Help architect solutions for power management of the SoC
- Write microarchitecture and/or design specifications for power management and other SoC level IPs
- Design, implement, and debug complex logic designs
- Integrate complex IPs into the SOC
- Support all front end integration activities like Lint, CDC, Synthesis, and ECO
- Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams
- Collaborate with software and systems teams to ensure a high quality product
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Preferred Qualifications
Experience writing specifications and converting them to design.
Experience with multiple clock domains and asynchronous interfaces.
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies.
Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
Ability to communicate optimally across all internal groups.
Familiarity with software and operating concepts a plus.
Familiarity with scripting languages like Perl, Python, or TCL a plus.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976