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Cmos Layout Design Engineer Jobs (NOW HIRING)

Teledyne FLIR LLC

Sr. ASIC Layout Design Engineer

Goleta, CA · On-site

$113K - $151K/yr

Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm ... Programming/scripting skills in SKILL, TCL, Shell, or Python Salary Range: $113,600.00-$151,400.000 ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA

... circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

... circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor ... Collaborate with layout engineer on whole chip layout integration and improvement by Cadence ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

Analog Devices, Inc.

$125 - $150/hr

We are looking for an experienced and detail-oriented SiP layout design engineer with strong expertise in laminate and PCB layout design for advanced semiconductor packaging applications. This role ...

Analog Devices

SiP Layout Design Engineer

Wilmington, MA · On-site

$116K - $160K/yr

We are looking for an experienced and detail-oriented SiP layout design engineer with strong expertise in laminate and PCB layout design for advanced semiconductor packaging applications. This role ...

Analogdevices

SiP Layout Design Engineer

Wilmington, MA · On-site

$116K - $160K/yr

We are looking for an experienced and detail-oriented SiP layout design engineer with strong expertise in laminate and PCB layout design for advanced semiconductor packaging applications. This role ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

... layout. As an Analog Design Engineer, you will: * Work on detailed transistor level design of analog and mixed signal circuits for CMOS image sensors. * Perform the whole chip simulation along with ...

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Cmos Layout Design Engineer information

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$45K

$120.8K

$185.5K

How much do cmos layout design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for cmos layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a CMOS Layout Design Engineer do?

A CMOS Layout Design Engineer is responsible for designing the physical layout of integrated circuits (ICs) using CMOS (Complementary Metal-Oxide-Semiconductor) technology. They translate circuit schematics into geometric representations that can be fabricated on silicon wafers. Their work involves using specialized software tools to ensure the design meets electrical, performance, and manufacturing requirements. The role requires attention to detail, knowledge of semiconductor processes, and collaboration with circuit designers to optimize layouts for performance, area, and power consumption.

What are some typical challenges a CMOS Layout Design Engineer faces during the design and verification process?

A CMOS Layout Design Engineer often encounters challenges such as optimizing layouts for area, performance, and power while adhering to strict design rules and manufacturing constraints. Ensuring that the design passes Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification can be particularly demanding, especially as circuit complexity increases. Collaboration with circuit designers is crucial to resolve issues like parasitic effects and signal integrity concerns, making strong communication skills essential. Staying updated with evolving process technologies and EDA tools is also an ongoing part of the role.

What are the key skills and qualifications needed to thrive as a CMOS Layout Design Engineer, and why are they important?

To thrive as a CMOS Layout Design Engineer, you need a solid understanding of semiconductor physics, CMOS process technology, and physical design principles, typically supported by a degree in electrical engineering or a related field. Expertise in Electronic Design Automation (EDA) tools such as Cadence Virtuoso, as well as knowledge of DRC/LVS verification, is essential. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with circuit designers and ensuring design accuracy. These skills are important because they ensure efficient, high-quality integrated circuit layouts that meet performance, manufacturability, and reliability standards.

What is the difference between Cmos Layout Design Engineer vs VLSI Design Engineer?

AspectCmos Layout Design EngineerVLSI Design Engineer
Primary FocusCreating physical layouts of CMOS circuitsDesigning entire VLSI chip architectures and logic
Skills RequiredLayout tools, CMOS fabrication process knowledgeHardware description languages, circuit design, verification
Work EnvironmentASIC/IC design teams, semiconductor fabsIntegrated circuit design teams, EDA tool usage

While both roles involve semiconductor design, a Cmos Layout Design Engineer specializes in the physical layout of CMOS circuits, focusing on placement and routing. In contrast, a VLSI Design Engineer oversees the entire chip design process, including logic design and verification. Both roles require knowledge of semiconductor processes and collaboration with fabrication teams, but their core responsibilities differ in scope and focus.

What are popular job titles related to Cmos Layout Design Engineer jobs?

For Cmos Layout Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Cmos Layout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

High-Speed Analog Layout Design Engineer

San Jose, CA • On-site

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$200K - $300K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Key responsibilities

  • Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification

  • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability

  • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification

Job description

Principal High-Speed Analog Layout Design Engineer
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
 
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
 
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
 
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
 
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
 
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
Annual Base Salary Range for US: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)