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Cmos Layout Design Engineer Jobs (NOW HIRING)

Nvidia

Senior Mask Layout Design Engineer

OR · On-site +1

Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity. We are looking for ... micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to ...

Apple Inc.

Digital Layout Design Engineer

San Diego, CA · On-site

$166K - $296K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

Staff Layout Design Engineer Experience Level: Professional Job Type: Regular Location: Raleigh, NC ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Intel

Analog Layout Design Engineer

Hillsboro, OR · On-site

$220K/yr

The Role and Impact Intel is seeking a passionate and skilled Analog Layout Design Engineer to join ... CMOS technologies and high-voltage rules * Floor planning and hierarchical layout planning for ...

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Qorvo, Inc.

Staff Layout Design Engineer

Sacramento, CA · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Qorvo, Inc.

Staff Layout Design Engineer

Austin, TX · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Qorvo, Inc.

Staff Layout Design Engineer

Denver, CO · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Qorvo, Inc.

Staff Layout Design Engineer

Tallahassee, FL · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC · On-site

$144K - $187K/yr

In this position, you will work closely with design engineering groups to complete the layout and ... Comfortable with CMOS and SOI technologies across multiple foundry PDKs * Demonstrated ability to ...

Cirrus Logic

IC Layout Design

Greensboro, NC · On-site

The Role In this position, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL ...

Teledyne

Sr. ASIC Layout Design Engineer

Goleta, CA · On-site

$113K - $151K/yr

Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm ... Programming/scripting skills in SKILL, TCL, Shell, or Python Salary Range: $113,600.00-$151,400.000 ...

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Cmos Layout Design Engineer information

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$45K

$120.8K

$185.5K

How much do cmos layout design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for cmos layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a CMOS Layout Design Engineer do?

A CMOS Layout Design Engineer is responsible for designing the physical layout of integrated circuits (ICs) using CMOS (Complementary Metal-Oxide-Semiconductor) technology. They translate circuit schematics into geometric representations that can be fabricated on silicon wafers. Their work involves using specialized software tools to ensure the design meets electrical, performance, and manufacturing requirements. The role requires attention to detail, knowledge of semiconductor processes, and collaboration with circuit designers to optimize layouts for performance, area, and power consumption.

What are some typical challenges a CMOS Layout Design Engineer faces during the design and verification process?

A CMOS Layout Design Engineer often encounters challenges such as optimizing layouts for area, performance, and power while adhering to strict design rules and manufacturing constraints. Ensuring that the design passes Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification can be particularly demanding, especially as circuit complexity increases. Collaboration with circuit designers is crucial to resolve issues like parasitic effects and signal integrity concerns, making strong communication skills essential. Staying updated with evolving process technologies and EDA tools is also an ongoing part of the role.

What are the key skills and qualifications needed to thrive as a CMOS Layout Design Engineer, and why are they important?

To thrive as a CMOS Layout Design Engineer, you need a solid understanding of semiconductor physics, CMOS process technology, and physical design principles, typically supported by a degree in electrical engineering or a related field. Expertise in Electronic Design Automation (EDA) tools such as Cadence Virtuoso, as well as knowledge of DRC/LVS verification, is essential. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with circuit designers and ensuring design accuracy. These skills are important because they ensure efficient, high-quality integrated circuit layouts that meet performance, manufacturability, and reliability standards.

What is the difference between Cmos Layout Design Engineer vs VLSI Design Engineer?

AspectCmos Layout Design EngineerVLSI Design Engineer
Primary FocusCreating physical layouts of CMOS circuitsDesigning entire VLSI chip architectures and logic
Skills RequiredLayout tools, CMOS fabrication process knowledgeHardware description languages, circuit design, verification
Work EnvironmentASIC/IC design teams, semiconductor fabsIntegrated circuit design teams, EDA tool usage

While both roles involve semiconductor design, a Cmos Layout Design Engineer specializes in the physical layout of CMOS circuits, focusing on placement and routing. In contrast, a VLSI Design Engineer oversees the entire chip design process, including logic design and verification. Both roles require knowledge of semiconductor processes and collaboration with fabrication teams, but their core responsibilities differ in scope and focus.

What are popular job titles related to Cmos Layout Design Engineer jobs?

For Cmos Layout Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Cmos Layout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Senior Mask Layout Design Engineer

OR • On-site, Remote

Nvidia
Computer and Electronic Product Manufacturing • 10K+ employees
Learn more about Nvidiaexternal

Full-time

Posted 12 days ago

Nvidia rating

9.6

Company rating: 9.6 out of 10

Based on 18 frontline employees who took The Breakroom Quiz

Job description

Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity. We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades.

Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world.

This is our life's work, to amplify human creativity and intelligence. Join our dynamic team today. What you'll be doing: The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers.

Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, power delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. Job duties will include floor planning, custom layout and verifying against design rules and schematics. Fill, post-processing, DRC mitigation, and foundry interactions What we need to see: BS in Electrical Engineering (or equivalent experience) At least 7+ years of hands-on layout design experience Deep understanding of analog circuit layout concepts in submicron CMOS technologies.

Validated experience with Cadence custom circuit design tools - particularly virtuoso Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre Leadership experience mentoring and assisting junior mask designers, implementing standard processes for the team, and keeping checklists for optimal layout design. Communicate with diverse team of mask designers across geographies and timezones. Ability to work optimally in a team, good interpersonal skills and positive energy.

Proficiency in scripting languages like perl, python, skill etc. is a plus. Knowledge of layout automation is a definite plus.

NVIDIA is a pioneer in bringing groundbreaking technology to new markets. We have some of the most forward-thinking and hardworking people in the world working with us. If you're creative and autonomous, we want to hear from you.

#LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until January 26, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

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