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Cmos Layout Design Engineer Jobs (NOW HIRING)

Aquila Technology

Circuit Design Engineer

Lexington, MA · Remote

Circuit Design Engineer Clearance Level: Must have an Active Secret Clearance to be considered for ... Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in ...

New

Aquila Technology

Circuit Design Engineer

Lexington, MA · Remote

Circuit Design Engineer Clearance Level: Must have an Active Secret Clearance to be considered for ... Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in ...

New

Superbeo

Analog Layout Design Engineer

Santa Clara, CA · On-site

Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Experience with layout of cutting-edge high-performance, high-speed CMOS integrated circuits in ...

Apple

Digital Layout Design Engineer

Austin, TX · On-site

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. -Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX · On-site

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. -Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Cirrus Logic

Layout Design Engineer

Austin, TX · On-site

The Role In this role, you will work closely with design engineering to complete the layout and verification of high-performance mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL and ...

Apple Inc.

Digital Layout Design Engineer

Beaverton, OR · On-site

$150 - $200/hr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.

Apple

Digital Layout Design Engineer

Austin, TX

$166K - $296K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$166K - $296K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$166K - $296K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

Apple

Digital Layout Design Engineer

Austin, TX

$166K - $296K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers ...

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Cmos Layout Design Engineer information

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$45K

$120.8K

$185.5K

How much do cmos layout design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for cmos layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a CMOS Layout Design Engineer do?

A CMOS Layout Design Engineer is responsible for designing the physical layout of integrated circuits (ICs) using CMOS (Complementary Metal-Oxide-Semiconductor) technology. They translate circuit schematics into geometric representations that can be fabricated on silicon wafers. Their work involves using specialized software tools to ensure the design meets electrical, performance, and manufacturing requirements. The role requires attention to detail, knowledge of semiconductor processes, and collaboration with circuit designers to optimize layouts for performance, area, and power consumption.

What are some typical challenges a CMOS Layout Design Engineer faces during the design and verification process?

A CMOS Layout Design Engineer often encounters challenges such as optimizing layouts for area, performance, and power while adhering to strict design rules and manufacturing constraints. Ensuring that the design passes Design Rule Checks (DRC) and Layout Versus Schematic (LVS) verification can be particularly demanding, especially as circuit complexity increases. Collaboration with circuit designers is crucial to resolve issues like parasitic effects and signal integrity concerns, making strong communication skills essential. Staying updated with evolving process technologies and EDA tools is also an ongoing part of the role.

What are the key skills and qualifications needed to thrive as a CMOS Layout Design Engineer, and why are they important?

To thrive as a CMOS Layout Design Engineer, you need a solid understanding of semiconductor physics, CMOS process technology, and physical design principles, typically supported by a degree in electrical engineering or a related field. Expertise in Electronic Design Automation (EDA) tools such as Cadence Virtuoso, as well as knowledge of DRC/LVS verification, is essential. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills for collaborating with circuit designers and ensuring design accuracy. These skills are important because they ensure efficient, high-quality integrated circuit layouts that meet performance, manufacturability, and reliability standards.

What is the difference between Cmos Layout Design Engineer vs VLSI Design Engineer?

AspectCmos Layout Design EngineerVLSI Design Engineer
Primary FocusCreating physical layouts of CMOS circuitsDesigning entire VLSI chip architectures and logic
Skills RequiredLayout tools, CMOS fabrication process knowledgeHardware description languages, circuit design, verification
Work EnvironmentASIC/IC design teams, semiconductor fabsIntegrated circuit design teams, EDA tool usage

While both roles involve semiconductor design, a Cmos Layout Design Engineer specializes in the physical layout of CMOS circuits, focusing on placement and routing. In contrast, a VLSI Design Engineer oversees the entire chip design process, including logic design and verification. Both roles require knowledge of semiconductor processes and collaboration with fabrication teams, but their core responsibilities differ in scope and focus.

What are popular job titles related to Cmos Layout Design Engineer jobs?

For Cmos Layout Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Cmos Layout Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Circuit Design Engineer

Lexington, MA • Remote

Aquila Technology
See more jobs at Aquila Technologyexternal

Part-time

Posted 2 days ago

New

Job description

Circuit Design Engineer

Clearance Level: Must have an Active Secret Clearance to be considered for this opportunity due to the nature of the work. Must be US Citizen 

Location: This role is 100% remote - must be willing to travel up to 3 times a year.

At Aquila Technology, you will see our team’s passion every day, whether we are building a robust, policy-compliant IT system or stress-testing a system to identify gaps and security vulnerabilities. To own the advantage, we ensure our team owns results and gets the work done right the first time by deploying smart, purposeful solutions that work. Aquila is the right people with the right skills driving the right outcomes. We call this the Aquila Advantage.

About the Role:

Aquila Technology is seeking a Circuit Design Engineer to support one of the nation’s premier defense research organizations. The team develops custom digital & mixed-signal Readout Integrated Circuits (ROICs) for advanced imager applications. An analog/mixed-signal layout design engineer is needed for implementation of imager circuit building blocks.

Must Have

  • Clearance Level: Currently holds a Secret Clearance (OR a higher clearance)
  • 10 years - Cadence IC design flow with layout, DRC, LVS, and parasitic extraction using Calibre and Assura
  • 10 years - Experience in top level floor planning as well as block level design
  • 10 years - Experience with multiple design tape outs
  • 10 years - Deep-submicron CMOS Layout (12nm - 22nm, Global Foundries)
  • Presentation, verbal and written communication skills
  • Strong team communication
  • Strong Verbal and Written Communication

Responsibilities include but are not limited to:

  • Physical layout and verification of integrated circuit building blocks
  • Full-chip assembly and top-level verification.
  • Use best-practices for managing local process variation through layout techniques as well as high-speed digital and RF layout techniques to minimize unwanted parasitic interactions.
Must Have:
  • Experience in deep-submicron CMOS layout across technologies including 12-65 nm design nodes in multiple foundries such as Global Foundries, onsemi and Tower Jazz
  • Cadence integrated circuit design flow including layout, DRC, LVS and parasitic extraction through the use of Calibre and Assura.
  • Proven track record of multiple design tape outs
  • Extensive experience in top level floor planning as well as block level design
  • Strong interpersonal and organizational skills along with strong written/verbal skills are required to support a multi-person design team in an effective way.

Work Location: Work from Home: This position is REMOTE. The candidate is able to work remotely from any location. They may be asked to take up to 3+ trips per calendar year to Lexington if the program/project requires it.
Core Work Hours: This position is a part time role with up to 24hrs a week.
Clearance Level: An ACTIVE clearance is required for this role. Do not submit candidates who do not meet this requirement.
Interview Process: 1st round will be a Zoom with the hiring manager. 2nd round will be a Zoom with additional team members as needed.

We are an Equal Opportunity Employer

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