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Asic Digital Design Jobs (NOW HIRING)

Phizenix

Digital Design Engineer

Santa Clara, CA

$159K/yr

: Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into ...

Phizenix

Digital Design Engineer

Santa Clara, CA · On-site

$180K - $250K/yr

: Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into ...

Navtech, Inc.

Digital Design Engineer.

$139K/yr

Digital Design Engineer. Location : REMOTE Duration : 6+ Months on W2 Visa : Independent candidates ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Understanding of digital design and verification practices. * Be able to take a specification ...

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All JobsAsic Digital Design Jobs

Asic Digital Design information

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$80.5K

$139.4K

$182.5K

How much do asic digital design jobs pay per year?

As of Aug 6, 2026, the average yearly pay for asic digital design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is the difference between Asic Digital Design vs FPGA Digital Design?

AspectAsic Digital DesignFPGA Digital Design
Required CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with ASIC design toolsBachelor's or Master's in Electrical Engineering or Computer Engineering; familiarity with FPGA development tools
Work EnvironmentDesigning custom chips in semiconductor labs or design housesImplementing and testing designs on FPGA boards in labs or development environments
Industry UsageSemiconductor companies, ASIC design firmsPrototyping, testing, and low-volume production in various industries

Asic Digital Design and FPGA Digital Design share foundational skills in digital logic and hardware description languages. However, Asic Digital Design focuses on creating custom integrated circuits for mass production, requiring detailed knowledge of ASIC fabrication processes. FPGA Digital Design involves programming reconfigurable hardware for testing and prototyping, offering more flexibility and faster deployment. Both roles are essential in hardware development but differ in application, tools, and end-use environments.

More about Asic Digital Design jobs
What cities are hiring for Asic Digital Design jobs? Cities with the most Asic Digital Design job openings:
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Asic Digital Design jobs near you
Infographic showing various Asic Digital Design job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

Digital Design Engineer

Phizenix

Santa Clara, CA

$159K/yr

Other

Posted 16 days ago

Job description

Job description :

Role Overview

We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into clean, high-quality RTL and drive it through synthesis and timing closure. Just as important, the ideal candidate leverages strong firmware coding experience to drive pre-silicon simulation, develop bare-metal diagnostics, and ensure seamless hardware-software integration-for example, writing firmware on an embedded RISC CPU IP to control on-chip analog hardware blocks and low-speed control/calibration loops for optical components. Strong digital ASIC fundamentals, paired with the ability to debug complex designs in emulation and on silicon, round out the profile.

Key Responsibilities

  • Develop micro-architecture and author high-quality, synthesizable RTL following best-in-class coding methods and design-for-verification / design-for-test practices.
  • Write firmware and bare-metal diagnostics on embedded RISC CPU IP to configure and control on-chip analog blocks and low-speed control/calibration loops for optical components.
  • Drive pre-silicon simulation and hardware-software co-verification, validating firmware against RTL well ahead of tape-out.
  • Integrate processor subsystems-including licensed CPU IP-AMBA fabrics, and serial/interconnect interfaces (e.g., PCIe, UCIe) into the SoC/ASIC.
  • Drive the full implementation flow: synthesis, timing constraints (SDC), timing closure, and equivalence checking (Formality / Conformal), with clean Lint / CDC / RDC signoff.
  • Build and run emulation environments; lead silicon bring-up sequences and post-silicon debug, root-causing and resolving issues on hardware.
  • Provide responsive support-triaging design problems and delivering timely solutions-and collaborate with analog/mixed-signal, DSP, verification, and physical-design teams.

Required Qualifications

Education & Experience

  • B.S. or M.S. in Electrical/Electronics or Computer Engineering (or related), with relevant digital ASIC design experience.
  • Demonstrated experience taking digital designs from RTL through synthesis, timing closure, and silicon bring-up.

Core Technical Skills

  • Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods.
  • Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g., RISC-V or Arm) to drive analog blocks and low-speed loops.
  • Knowledge of AMBA and serial protocols, processors, and silicon bring-up sequences.
  • Strong design, emulation, and silicon debug skills, with proven hardware-software integration experience.
  • Expertise in synthesis, constraints, timing closure, and equivalence checks (Formality / Conformal).
  • Experience with Lint / CDC / RDC tools.

Professional Skills

  • Customer-support orientation and excellent communication and oratory skills.

Preferred Qualifications

  • Familiarity with interconnect protocols such as PCIe (Gen5/6/7) and UCIe.
  • Experience integrating vendor CPU IP and developing the associated firmware, drivers, and diagnostics.
  • High-speed wireline / SerDes-based SoC experience; UPF low-power design, DFT, and scan/ATPG flows.
  • Scripting proficiency (Python, Tcl)

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