Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA) * Utilize industry-standard ASIC design tools for lint ...
Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA) * Utilize industry-standard ASIC design tools for lint ...
Digital Design Engineer.
$139K/yr
Digital Design Engineer. Location : REMOTE Duration : 6+ Months on W2 Visa : Independent candidates ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...
Digital Design Engineer.
$139K/yr
Digital Design Engineer. Location : REMOTE Duration : 6+ Months on W2 Visa : Independent candidates ... Role responsibilities (including, but not limited to): • Own an ASIC IP RTL implementation for IP ...
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, CA · On-site
Bachelor's or Masters degree in Science, Engineering, or related field. * 5+ years ASIC design, RTL coding, front-end digital design experience * 3+ years Hardware Architecture experience Preferred ...
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, CA · On-site
Bachelor's or Masters degree in Science, Engineering, or related field. * 5+ years ASIC design, RTL coding, front-end digital design experience * 3+ years Hardware Architecture experience Preferred ...
Digital Design Engineer
Santa Clara, CA · On-site
$159K/yr
Digital Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type ... Able to actively participate during various phases of the ASIC/SOC design process -Architecture ...
Quick apply
Digital Design Engineer
Santa Clara, CA · On-site
$159K/yr
Digital Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type ... Able to actively participate during various phases of the ASIC/SOC design process -Architecture ...
Digital Design Engineer
San Diego, CA · On-site
$115K - $173K/yr
Qualcomm's high speed parallel interfaces team is looking for a motivated and driven ASIC front end ... The Digital Design Engineer will be responsible for designing, developing RTL, and implementing ...
Digital Design Engineer
San Diego, CA · On-site
$115K - $173K/yr
Qualcomm's high speed parallel interfaces team is looking for a motivated and driven ASIC front end ... The Digital Design Engineer will be responsible for designing, developing RTL, and implementing ...
AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL CIRCUITS Position Overview: We are looking for an experienced ASIC Design Engineer with a strong background in the design, verification, and ...
AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL CIRCUITS Position Overview: We are looking for an experienced ASIC Design Engineer with a strong background in the design, verification, and ...
ASIC/FPGA Design Manager
North Reading, MA · On-site
$126K - $173K/yr
ASIC/FPGA Design Manager Background Our client is seeking an experienced FPGA Design Manager to ... These platforms leverage high-performance digital systems, high-speed interfaces, data acquisition ...
ASIC/FPGA Design Manager
North Reading, MA · On-site
$126K - $173K/yr
ASIC/FPGA Design Manager Background Our client is seeking an experienced FPGA Design Manager to ... These platforms leverage high-performance digital systems, high-speed interfaces, data acquisition ...
We're hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education, skills, and market ...
We're hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education, skills, and market ...
Senior Principal Engineer Digital ASIC Design/Manager
San Diego, CA · On-site
$214K - $348K/yr
We're hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education, skills, and market ...
Senior Principal Engineer Digital ASIC Design/Manager
San Diego, CA · On-site
$214K - $348K/yr
We're hiring a Senior Principal Engineer Digital ASIC Design at our San Diego, CA facility! Salary Range: $214,000 - 348,000 annually (Final offer based on experience, education, skills, and market ...
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built ...
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built ...
ASIC Design Engineer, ML Processor & Digital IP
San Jose, CA · On-site
$124K/yr
As a frontend ASIC Design Engineer, ML Processor & Digital IP you will work on defining and implementing features in key IPs.. THE PERSON: You have a passion for modern, complex processor ...
ASIC Design Engineer, ML Processor & Digital IP
San Jose, CA · On-site
$124K/yr
As a frontend ASIC Design Engineer, ML Processor & Digital IP you will work on defining and implementing features in key IPs.. THE PERSON: You have a passion for modern, complex processor ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
Job Title: Sr. Digital ASIC Engineer Posting Start Date: 6/9/26 Job Location(s): Hillsboro If you ... Responsibilities You will architect, design and collaborate on radio subsystems in small geometry ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
Job Title: Sr. Digital ASIC Engineer Posting Start Date: 6/9/26 Job Location(s): Hillsboro If you ... Responsibilities You will architect, design and collaborate on radio subsystems in small geometry ...
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built ...
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC team. The role is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Understanding of digital design and verification practices. * Be able to take a specification ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Understanding of digital design and verification practices. * Be able to take a specification ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
Responsibilities You will architect, design and collaborate on radio subsystems in small geometry ... Emulation, modeling, simulation, silicon testing and debugging of digital circuits and SOCs
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
Responsibilities You will architect, design and collaborate on radio subsystems in small geometry ... Emulation, modeling, simulation, silicon testing and debugging of digital circuits and SOCs
Prior experience in ASIC Design and DV is a plus. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation ...
Prior experience in ASIC Design and DV is a plus. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis ... Familiarity with ASIC design flow, and experience with ASIC design tools. * Knowledge of low-power ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis ... Familiarity with ASIC design flow, and experience with ASIC design tools. * Knowledge of low-power ...
Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing concepts. * Excellent problem-solving and analytical skills. * Ability to work collaboratively in a fast ...
Quick apply
Proficiency in FPGA and ASIC design tools. * Strong understanding of digital signal processing concepts. * Excellent problem-solving and analytical skills. * Ability to work collaboratively in a fast ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis ... Familiarity with ASIC design flow, and experience with ASIC design tools. * Knowledge of low-power ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Design and implement digital circuits using HDL (Verilog/ System Verilog). * Perform synthesis ... Familiarity with ASIC design flow, and experience with ASIC design tools. * Knowledge of low-power ...
Principal ASIC Design Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC ...
Principal ASIC Design Engineer
Saint Paul, MN · On-site
$200K - $220K/yr
FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC ...
Asic Digital Design information
See salary details
$80.5K - $89.8K
0% of jobs
$89.8K - $99K
0% of jobs
$99K - $108.3K
1% of jobs
$108.3K - $117.6K
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$117.6K - $126.9K
0% of jobs
$130.7K is the 25th percentile. Wages below this are outliers.
$126.9K - $136.1K
57% of jobs
$140.1K is the 75th percentile. Wages above this are outliers.
$136.1K - $145.4K
38% of jobs
$145.4K - $154.7K
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$154.7K - $164K
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$164K - $173.2K
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$173.2K - $182.5K
1% of jobs
$80.5K
$139.4K
$182.5K
How much do asic digital design jobs pay per year?
What is the difference between Asic Digital Design vs FPGA Digital Design?
| Aspect | Asic Digital Design | FPGA Digital Design |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with ASIC design tools | Bachelor's or Master's in Electrical Engineering or Computer Engineering; familiarity with FPGA development tools |
| Work Environment | Designing custom chips in semiconductor labs or design houses | Implementing and testing designs on FPGA boards in labs or development environments |
| Industry Usage | Semiconductor companies, ASIC design firms | Prototyping, testing, and low-volume production in various industries |
Asic Digital Design and FPGA Digital Design share foundational skills in digital logic and hardware description languages. However, Asic Digital Design focuses on creating custom integrated circuits for mass production, requiring detailed knowledge of ASIC fabrication processes. FPGA Digital Design involves programming reconfigurable hardware for testing and prototyping, offering more flexibility and faster deployment. Both roles are essential in hardware development but differ in application, tools, and end-use environments.

Full-time
Posted 18 days ago
Qualcomm rating
9.6
Based on 5 frontline employees who took The Breakroom Quiz
5th of 191 rated software companies
Job description
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for integration across Qualcomm's product portfolio.
In this role, you will collaborate with a cross-functional team to architect, design, implement, and validate complex IP blocks. Your work will directly support multiple business units and require a strong grasp of the full ASIC design flow, from RTL through GDSII, along with an understanding of the challenges associated with advanced semiconductor technologies.
Responsibilities:
- Architect and define the digital design of Mixed-Signal IPs (e.g., DAC, ADC, PLL) in close collaboration with system architecture and analog design teams
- Develop micro-architecture and implement RTL for complex mixed-signal IP blocks
- Apply advanced techniques in computer architecture, digital signal processing, and ASIC design to enhance power, performance, and area (PPA)
- Utilize industry-standard ASIC design tools for lint checking, clock domain crossing (CDC) analysis, design-for-test (DFT), synthesis, formal verification (FV), and static timing analysis (STA)
- Design and analyze DFT logic, including ATPG for stuck-at fault (SAF) and transition delay fault (TDF) coverage
- Create comprehensive design documentation, including hardware specifications
- Collaborate with the design verification (DV) team to define test plan, verify the design, and fix bugs
- Work with the physical design (PD) team to support floorplanning, placement, and timing closure of IPs
- Support SoC integration and debug, including pre-silicon simulation and post-silicon bring-up
Required for this Role:
- Master's degree in Electrical Engineering, Computer Engineering, or a related field
- 3+ years of experience in RTL and ASIC design
- Proficiency with industry-standard front-end ASIC design tools including VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, Spyglass, and others
Preferred Qualifications:
- Ph.D. in Electrical Engineering with 5+ years of industry experience in high-speed digital circuit design
- Strong background in low-power digital design techniques
- 2+ years of hands-on experience in RTL design and ASIC implementation of mixed-signal IPs such as SerDes DDR PHY, PLLs, DACs, ADCs, and sensors
- Expertise in computer architecture, digital signal processing, and algorithm development
- Experience developing automation scripts and design productivity tools using Python or Perl
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits:
$115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
About Qualcomm
Sourced by ZipRecruiter
Qualcomm is enabling a world where everyone and everything can be intelligently connected. You interact with products and technologies made possible by Qualcomm every day, including 5G-enabled smartphones that double as pro-level cameras and gaming devices, smarter vehicles and cities, and the technology behind the smart, connected factories that manufactured your latest purchase. Our powerful connectivity solutions keep you connected—even in remote areas. Qualcomm 5G and AI innovations are the power behind the connected intelligent edge. You’ll find our technologies behind and inside the innovations that deliver significant value across multiple industries and to billions of people every day.
Industry
Technology, communication and media
Company size
10,000+ Employees
Headquarters location
San Diego, CA, US
Year founded
1985