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Asic Design Verification Engineer Internship Jobs

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

... engineering/related degree + 1 year of related experience. * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools.

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Experience in scripting (Python, Perl) and C/C++ programming language. Preferred Qualifications

AvicenaTech

ASIC Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$165K - $241K/yr

... engineering/related degree + 1 year of related experience. * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools.

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$152K - $219K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

Cisco

ASIC Design Verification Engineer

San Jose, CA

$165K - $241K/yr

Influence ASIC architecture and design to enable robust verification and high-quality silicon ... Experience in scripting (Python, Perl) and C/C++ programming language. Preferred Qualifications

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$123K - $174K/yr

Your Impact As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco's revolutionary data center solutions. You'll architect and develop DV infrastructure, create ...

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All JobsAsic Design Verification Engineer Internship Jobs

Asic Design Verification Engineer Internship information

See salary details

$105.5K

$149.2K

$167K

How much do asic design verification engineer internship jobs pay per year?

As of Jun 9, 2026, the average yearly pay for asic design verification engineer internship in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What does an ASIC Design Verification Engineer Intern do?

An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer Intern, and why are they important?

To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.

What are some typical challenges faced during an ASIC Design Verification Engineer Internship, and how can interns effectively address them?

Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.

What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?

AspectAsic Design Verification Engineer InternshipAsic Design Engineer
CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's degree in Electrical Engineering or related field
Work EnvironmentInternship program, often in a corporate R&D or design teamFull-time professional role in ASIC design teams
ResponsibilitiesAssisting in verification testbenches, running simulations, learning verification toolsDesigning, implementing, and testing ASIC hardware components
DurationUsually 3-6 monthsFull-time ongoing role

The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.

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Asic Design Verification Engineer Internship jobs near you

SoC/ASIC Design Verification Engineer

zeroRISC

Boston, MA

Full-time

Posted 25 days ago

Job description

zeroRISC
 
zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they’re built or where they’re deployed.
 
Role Overview
 
As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate and solidify zeroRISC's status as the leading provider of secure silicon IP by developing essential verification collateral. You will interact directly with zeroRISC customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere. We're looking for engineers with strong design verification skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.
Key Responsibilities:
  • Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off
  • Build high quality verification environments at the chip/top and block levels following engineering best practices
  • Write thorough verification documentation including test plans
  • Diagnose, debug, and resolve regression failures and other errors
  • Achieve coverage closure
  • Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers
What We’re Looking For:
  • Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
  • 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools
  • Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments
Preferred Qualifications (not required):
  • Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
  • Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)
  • Knowledge of computer architecture and memory subsystem architectures
  • Experience verifying low power designs
  • Experience with scripting languages such as Python
Why Join Us?
  • Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments
  • As a seed-stage startup, this role offers significant opportunities for learning and career growth
  • Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.