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Ai Chip Design Rtl Jobs in Texas (NOW HIRING)

... our RTL-to-GDS implementation flows. You will be directly responsible for creating AI-powered ... AI applications for EDA or chip design Minimum Qualifications Experience with GenAI frameworks ...

... our RTL-to-GDS implementation flows. You will be directly responsible for creating AI-powered ... AI applications for EDA or chip design Minimum Qualifications Experience with GenAI frameworks ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

SOC Timing Analysis (STA) Engineer ,HBM

Richardson, TX · On-site

$123K - $127K/yr

... chip-level static timing sign-off for next-generation die. You will work closely with RTL design ... AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application ...

Mythic is building the future of AI computing with breakthrough analog technology that delivers ... RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom ...

About Us: Mythic is building the future of AI computing with breakthrough analog technology that ... RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom ...

About Us: Mythic is building the future of AI computing with breakthrough analog technology that ... RTL Design at Mythic: At Mythic, our RTL design team is at the heart of transforming our custom ...

CPU Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... with architecture and RTL designers on verifying the functional correctness of the design • ...

CPU Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

In this highly visible role, you will be at the center of a chip design effort collaborating with ... with architecture and RTL designers on verifying the functional correctness of the design • ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

GPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to ...

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application ...

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Ai Chip Design Rtl information

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What cities in Texas are hiring for Ai Chip Design Rtl jobs? Cities in Texas with the most Ai Chip Design Rtl job openings:
Infographic showing various Ai Chip Design Rtl job openings in Texas as of June 2026, with employment types broken down into 94% Full Time, 4% Part Time, 1% Temporary, and 1% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution.
GenAI Physical Synthesis Engineer

GenAI Physical Synthesis Engineer

Apple

Austin, TX

$147K - $272K/yr

Full-time

Medical, Dental, Retirement

Posted 11 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 661 frontline employees who took The Breakroom Quiz

6th of 30 rated technology retailers


Job description

Do you love building intelligent solutions that revolutionize chip design? Do you see the transformative potential of GenAI in physical synthesis workflows? As part of our Silicon Technologies group, you'll pioneer the next generation of AI-powered design automation tools that will accelerate our processor and SoC development. You'll harness cutting-edge GenAI and agentic technologies to solve complex physical synthesis challenges, enabling Apple to deliver even more powerful and efficient silicon. Joining this team means you'll be at the forefront of merging artificial intelligence with chip design, creating intelligent agents that will reshape how we build the technology that powers Apple's beloved devices!
Description
You will apply your expertise in GenAI, agentic frameworks, and physical synthesis to develop intelligent automation solutions that transform our RTL-to-GDS implementation flows. You will be directly responsible for creating AI-powered agents using technologies like Model Context Protocol (MCP) that can autonomously optimize physical synthesis processes, predict design challenges, and recommend solutions.","responsibilities":"Design and develop GenAI-powered agentic applications for physical synthesis optimization and automation
Implement intelligent agents using Model Context Protocol (MCP) and other agentic frameworks to enhance synthesis flows
Create AI-driven solutions that can autonomously analyze and optimize Physical Synthesis, LEC and DFT Implementation workflows
Build intelligent CAD tools that leverage GenAI for synthesis optimization and automated debugging
Integrate agentic solutions with existing EDA tools (Fusion Compiler, Genus) to create seamless AI-enhanced workflows
Collaborate with cross-functional teams to deploy AI agents across multiple design teams and synthesis flows
Preferred Qualifications
Understanding of physical synthesis concepts and CAD flows
Experience in Python AI/ML libraries (PyTorch, TensorFlow, Transformers) and MCP or similar agentic frameworks
Experience developing AI agents or autonomous systems for technical domains
Knowledge of prompt engineering, RAG (Retrieval-Augmented Generation), and fine-tuning techniques
Experience with agentic AI frameworks beyond MCP (AutoGen, CrewAI, LangChain agents, etc.)
Background in CAD flow or frontend methodology development combined with AI/ML expertise
Experience with Low Power implementation flows (UPF) and AI-driven power optimization
Familiarity with logical equivalence tools (Conformal LEC, Formality) and opportunities for AI enhancement
Knowledge of static timing analysis, place and route tools, and potential AI applications in these domains
Experience with cloud platforms and distributed AI model deployment
Publications or demonstrated expertise in AI applications for EDA or chip design
Minimum Qualifications
Experience with GenAI frameworks, large language models, and AI agent development
Experience with industry standard Synthesis tools such as Fusion Compiler or Genus
Scripting skills in TCL, Python, or Perl for EDA tool automation
Minimum requirement of BS + 3 years of relevant industry experience
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $147,400 and $272,100, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976