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Ai Chip Design Rtl Jobs in Oregon (NOW HIRING)

K2 Space

OR

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Support chip bring-up and debug through close collaboration with post-silicon and test teams.

Nvidia

Senior CPU Design Engineer

Hillsboro, OR · Hybrid

Implement in RTL and coordinate execution with the verification team to ensure that the design is ... Support hardware engineering activities including chip floor plan, power/clock distribution, chip ...

Intel

Physical Design Engineer for Core IP

Hillsboro, OR · On-site

$148K - $152K/yr

Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart ... Performs physical design implementation of custom CPU designs from RTL to GDS to create a design ...

Nvidia

Senior VLSI CAD Software Engineer

Hillsboro, OR

$133K - $175K/yr

... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC ...

Apple

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

... RTL to delivery of our final GDSII. Your responsibilities include but are not limited to ... Generate block/chip level static timing constraints. Build full chip floor-plan including pin ...

Intel Corporation

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $200K/yr

In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions ... Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ...

Intel

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $200K/yr

In this role, you will pioneer the development of cutting-edge System-on-Chip (SoC) solutions ... Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ...

K2 Space

OR · On-site

$130K - $200K/yr

... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

K2 Space

OR

$130K - $200K/yr

... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

Intel

Collateral Device Engineer

Hillsboro, OR · On-site

Design and develop comprehensive device collateral including test chip architectures and product ... leadership for the AI era, enabling our customers to design leadership products, global ...

New

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an ... RTL coding and verification * Memory Controller + PHY integration and verification * Customer ...

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Ai Chip Design Rtl information

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Ai Chip Design Rtl jobs near you

Principal ASIC Physical Design Engineer

K2 Space

OR

$190K - $280K/yr

Other

Medical, Dental, Vision, Life, PTO

Posted yesterday

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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