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Dram Design Engineer Jobs in Oregon (NOW HIRING)

Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

Tualatin, OR · On-site

$123K - $196K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We are looking for an FPGA Design Engineer with exceptional technical skills and a strong desire to ... Architect and implement FPGA solutions to support next generation Flash and DRAM test ...

Teradyne

FPGA Design Engineer (MTD, Tualatin, OR)

Tualatin, OR · On-site

$123K - $196K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We are looking for an FPGA Design Engineer withexceptional technical skills and a strong desire to ... Architect and implement FPGA solutions to support next generation Flash and DRAM test ...

Rambus

Design Verification Principal Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

Rambus

Design Verification Principal Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple Inc.

Design Verification Engineer

Beaverton, OR · On-site

$110 - $170/hr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... Neural Engine hardware, DRAM subsystem, memory controller logic, Encode and Decode systems for ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Rambus

Design Verification Principal Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

  • Medical

  • Dental

  • Retirement

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

Apple

Design Verification Engineer

Beaverton, OR

$184K - $324K/yr

  • Medical

  • Dental

  • Retirement

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

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Dram Design Engineer information

What does a DRAM design engineer do?

A DRAM Design Engineer is responsible for designing and developing Dynamic Random Access Memory (DRAM) chips used in computers, mobile devices, and other electronic products. Their work includes creating circuit layouts, optimizing memory performance, and ensuring power efficiency and reliability. They collaborate with cross-functional teams, run simulations, and support the manufacturing process to ensure the final products meet industry standards.

What are some common challenges a DRAM design engineer faces during the memory development cycle?

DRAM Design Engineers often encounter challenges related to optimizing speed, power consumption, and reliability while adhering to strict specifications. Balancing these competing requirements can be complex, especially as process nodes shrink and memory densities increase. Additionally, ensuring signal integrity and minimizing noise in high-speed circuits requires close collaboration with layout, verification, and product engineering teams. Staying up to date with evolving industry standards and debugging unexpected issues during silicon validation are also key aspects of the role.

What are the key skills and qualifications needed to thrive as a DRAM design engineer, and why are they important?

To thrive as a DRAM Design Engineer, you need a solid background in electrical engineering, digital circuit design, and semiconductor physics, usually supported by a relevant engineering degree. Proficiency with hardware description languages (such as Verilog or VHDL), CAD tools, and simulation software is essential, along with familiarity with industry standards like JEDEC. Strong analytical thinking, attention to detail, and effective teamwork set top performers apart in this role. These skills ensure the development of reliable, high-performance memory products that meet stringent industry specifications and market demands.

What are popular job titles related to Dram Design Engineer jobs in Oregon?

For Dram Design Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Dram Design Engineer jobs in Oregon look for?

The top searched job categories for Dram Design Engineer jobs in Oregon are:

What cities in Oregon are hiring for Dram Design Engineer jobs?

Cities in Oregon with the most Dram Design Engineer job openings:

Dram Design Engineer jobs near you
Infographic showing various Dram Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 86% Full Time, 8% Part Time, and 6% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution.

Senior FPGA Design Engineer (MTD, Tualatin, OR)

Teradyne

Tualatin, OR • On-site

$154.90 - $247.80/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Location: Tualatin, OR; San Jose, CA, US

Opportunity Overview

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting‑edge memory test solutions. MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state‑of‑the‑art digital and analog designs, cutting‑edge ASIC/FPGA technologies, liquid cooling, and high‑performance signal delivery.

Responsibilities
  • Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
  • Provide technical guidance to junior engineers.
  • Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
  • Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
  • Maintain schedule commitments and deliver high quality end products.
  • Occasional travel may be required.
Qualifications
  • B.S. or M.S. in Electrical Engineering or closely related discipline and 8+ years of relevant work experience.
  • Experience with Digital Design and Architecture.
  • RTL coding, synthesis, timing closure and lab validation.
  • Experience with Static Timing Analysis of ASICs or FPGAs.
  • Experience with digital simulation testbench creation.
  • Experience with C or C++.
  • Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.
Desired Skills
  • FPGA Transceiver based design experience.
  • Experience with DRAM and Flash Memory interfaces.
  • Experience with Intel/Xilinx FPGA tool flows.
  • Proficiency with Verilog HDL Language.
  • Familiarity with UVM Methodology.
  • Linux and Windows operating systems experience.
  • Familiarity with ATE instrumentation.
Compensation

The base salary range for this role is $154,900–$247,800. This range is a good faith estimate and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

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