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Dram Design Engineer Jobs in Portland, OR (NOW HIRING)

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$184K - $324K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$184K - $324K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Apple

Design Verification Engineer

Beaverton, OR

$184K - $324K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... DRAM subsystem, memory controller logic - Encode and Decode systems for ProRes and other codec ...

Rambus

SMTS Verification Engineering

Hillsboro, OR · On-site

$108K - $201K/yr

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

New

Rambus

SMTS Verification Engineering

Hillsboro, OR · Hybrid

$108K - $201K/yr

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

New

Rambus

SMTS Verification Engineering

Hillsboro, OR · Hybrid

$108K - $201K/yr

... Design Verification Engineer to join our Memory Controller IP team in Hillsboro, Oregon. The ... Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working ...

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Showing results 1-20

All JobsDram Design Engineer JobsDram Design Engineer Jobs in Portland, OR

Dram Design Engineer information

See Portland, OR salary details

$43K

$93.5K

$168.1K

How much do dram design engineer jobs pay per year?

As of Jul 30, 2026, the average yearly pay for dram design engineer in Portland, OR is $93,483.00, according to ZipRecruiter salary data. Most workers in this role earn between $72,100.00 and $104,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DRAM Design Engineer, and why are they important?

To thrive as a DRAM Design Engineer, you need a solid background in electrical engineering, digital circuit design, and semiconductor physics, usually supported by a relevant engineering degree. Proficiency with hardware description languages (such as Verilog or VHDL), CAD tools, and simulation software is essential, along with familiarity with industry standards like JEDEC. Strong analytical thinking, attention to detail, and effective teamwork set top performers apart in this role. These skills ensure the development of reliable, high-performance memory products that meet stringent industry specifications and market demands.

What does a DRAM Design Engineer do?

A DRAM Design Engineer is responsible for designing and developing Dynamic Random Access Memory (DRAM) chips used in computers, mobile devices, and other electronic products. Their work includes creating circuit layouts, optimizing memory performance, and ensuring power efficiency and reliability. They collaborate with cross-functional teams, run simulations, and support the manufacturing process to ensure the final products meet industry standards.

What are some common challenges a DRAM Design Engineer faces during the memory development cycle?

DRAM Design Engineers often encounter challenges related to optimizing speed, power consumption, and reliability while adhering to strict specifications. Balancing these competing requirements can be complex, especially as process nodes shrink and memory densities increase. Additionally, ensuring signal integrity and minimizing noise in high-speed circuits requires close collaboration with layout, verification, and product engineering teams. Staying up to date with evolving industry standards and debugging unexpected issues during silicon validation are also key aspects of the role.
What are popular job titles related to Dram Design Engineer jobs in Portland, OR? For Dram Design Engineer jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Dram Design Engineer jobs in Portland, OR look for? The top searched job categories for Dram Design Engineer jobs in Portland, OR are:
Dram Design Engineer jobs near you
Infographic showing various Dram Design Engineer job openings in Portland, OR as of July 2026, with employment types broken down into 85% Full Time, 11% Part Time, and 4% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $93,483 per year, or $44.9 per hour.

FPGA Design Engineer (MTD, Tualatin, OR)

Teradyne

Tualatin, OR • On-site

$123K - $196K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 17 days ago

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose  
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day. 
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. 

Opportunity Overview 

Teradyne's Memory Test Division (MTD) seeks amotivated and technically driven FPGA Engineerto support the development of our growing portfolio of cutting-edge memory test solutions. 

MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world's most advanced memory technologies, combiningstate-of-the-art digital and analog designs,cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. 

We are looking for an FPGA Design Engineer withexceptional technical skills and a strong desire to collaborate on team-oriented projects. Success in this role means delivering high-quality, reliable products to market quickly. If you are excited to join a dynamic, global team, Teradyne may be the place for you! 

  • Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation. 

  • Provide technical guidance to junior engineers 

  • Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs. 

  • Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements. 

  • Maintain schedule commitments and deliver high quality end products. 

  • Occasional travel may be required. 

All About You 
We seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position. 

  • Bachelor's Degree or equivalent in Electrical Engineering or a closely related field with a minimum of 5 years of relevant work experience, or Master's Degree or equivalent with a minimum of 3 years of relevant work experience. 

  • Experience with Digital Design and Architecture 

  • RTL coding, synthesis, timing closure and lab validation 

  • Experience with Static Timing Analysis of ASICs or FPGAs 

  • Experience with digital simulation testbench creation 

  • Experience with C or C++ 

  • Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators. 

Addiiotnal Desired Skills:

  • FPGA Transceiver based design experience 

  • Experience with DRAM and Flash Memory interfaces 

  • Experience with Altera/AMD FPGA tool flows 

  • Proficiency with Verilog HDL Language 

  • Familiarity with UVM Methodology 

  • Scripting languages experience  

  • Linux and Windows operating systems experience 

  • Familiarity with ATE instrumentation 

Compensation: 
The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.  

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.   

Benefits: 

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details.  

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