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Asic Design Verification Engineer Jobs (NOW HIRING)

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA

$114K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Austin, TX

$114K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Ericsson

ASIC Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work schedule Your Work Powers the World's 5G Networks Not a simulation. Not a demo environment.

Positron AI

ASIC Design Verification Engineer

$200K - $350K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for ...

Qualcomm

ASIC Design Verification Engineer

Santa Clara, CA · On-site

$107K - $161K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Ericsson

ASIC Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Dental

  • Life

  • Retirement

  • PTO

ASIC Design Verification Engineer Austin, Texas This is not a remote work opportunity Hybrid work schedule Your Work Powers the World's 5G Networks Not a simulation. Not a demo environment.

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$165K - $241K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... engineering/related degree + 1 year of related experience. * Experience in System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools.

K2 Space

Senior ASIC Design Verification Engineer

Seattle, WA

$170K - $250K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

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ASIC Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do asic design verification engineer jobs pay per year?

As of Aug 17, 2026, the average yearly pay for asic design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by an ASIC Design Verification Engineer, and how can they be overcome?

ASIC Design Verification Engineers often encounter challenges such as managing complex verification environments, ensuring thorough coverage, and keeping up with tight project deadlines. Debugging failures in large, intricate designs can be time-consuming and requires strong problem-solving skills. To overcome these challenges, engineers typically rely on robust verification methodologies (such as UVM), effective communication within cross-functional design teams, and continuous learning to stay updated with the latest verification tools and techniques. Collaboration with designers and regular code reviews also help in identifying and resolving issues early in the development cycle.

What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer, and why are they important?

To thrive as an ASIC Design Verification Engineer, you need a solid understanding of digital design, verification methodologies (such as UVM or OVM), and a degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (like ModelSim or VCS), and scripting languages (such as Python or Perl) is essential, along with experience using version control systems. Strong problem-solving skills, attention to detail, and effective communication are crucial for identifying design issues and collaborating with cross-functional teams. These skills ensure accurate verification, reduce time-to-market, and contribute to the delivery of reliable and high-performance ASIC products.

What does an ASIC Design Verification Engineer do?

An ASIC Design Verification Engineer is responsible for ensuring that application-specific integrated circuits (ASICs) function as intended before they are manufactured. They develop and implement verification plans, create testbenches, and run simulations to identify design errors. Their work involves using hardware description languages (HDLs) like Verilog or VHDL and tools such as UVM to systematically verify design functionality. This role is crucial for catching bugs early, reducing costly mistakes in silicon, and improving product reliability.

What is the difference between Asic Design Verification Engineer vs Asic Design Engineer?

AspectAsic Design Verification EngineerAsic Design Engineer
Primary FocusVerifying the functionality of ASIC designs through testing and simulationDesigning and developing ASIC hardware components and architecture
Skills & CertificationsKnowledge of verification tools, scripting, hardware description languages (HDL), and testing methodologiesProficiency in HDL, digital design, and circuit architecture
Work EnvironmentMostly in verification labs, simulation environments, and testing setupsDesign offices, hardware labs, and development teams
Industry UsageCommonly employed in semiconductor and electronics companies for testing ASICsUsed in chip design companies for creating hardware components

In summary, Asic Design Verification Engineers focus on testing and validating ASIC designs to ensure functionality, while Asic Design Engineers are responsible for creating and developing the ASIC hardware itself. Both roles require knowledge of HDL and are integral to the ASIC development process.

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ASIC Design Verification Engineer jobs near you
Infographic showing various Asic Design Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 88% Full Time, 6% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

ASIC Engineer, Design Verification

Meta

Sunnyvale, CA • On-site, Remote

$146K/yr

Full-time

Re-posted 15 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

136th of 244 rated software companies

Job description

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.
ASIC Engineer, Design Verification Responsibilities:
  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Minimum Qualifications:
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Preferred Qualifications:
  • Experience working across and building relationships with cross-functional design, model and emulation teams
  • Experience with revision control systems like Mercurial(Hg), Git or SVN
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
  • Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
  • Track record of 'first-pass success' in ASIC development cycles
  • Experience with micro-architectural performance verification
  • Experience verifying GPU/CPU designs
  • Experience with verification of ARM/RISC-V based sub-systems or SoCs
  • Experience in development of UVM based verification environments from scratch
  • Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet
  • Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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