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Work From Home Rtl Design Engineer Jobs in Oregon

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

The Jernigan Agency

WORK FROM HOME

Bend, OR · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

IQVIA

Work from Home

Portland, OR · Remote

$18/hr

We are excited to announce that currently we are looking for a 100% remote (work from home-WFH) contract Pharmacy Support Call Center Representative to join our team. In this position, you will ...

The Jernigan Agency

WORK FROM HOME

Lake Oswego, OR · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

K2 Space

Senior ASIC Emulation Engineer

OR · On-site +1

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

... full physical design flow-from synthesis to GDSII-working closely with architecture, RTL ... Work with external physical design service providers and internal leads to review deliverables ...

HMG Careers

Work From Home Sales Specialist

Beaver, OR · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

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Work From Home Rtl Design Engineer information

See Oregon salary details

$42.8K

$93.2K

$167.6K

How much do work from home rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for work from home rtl design engineer in Oregon is $93,199.00, according to ZipRecruiter salary data. Most workers in this role earn between $71,900.00 and $104,100.00 per year, depending on experience, location, and employer.

What is a work from home RTL design engineer?

A Work From Home RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like Verilog or VHDL, all while working remotely. They develop RTL code for FPGA or ASIC designs, perform functional verification, and collaborate with hardware and software teams to ensure proper integration. This role requires strong knowledge of digital design principles, low-power design techniques, and simulation tools. Working remotely, engineers communicate via online tools, participate in virtual design reviews, and manage tasks independently while ensuring design quality and meeting project deadlines.

What are the key skills and qualifications needed to thrive as a work from home RTL design engineer?

A Work From Home RTL Design Engineer requires a thorough understanding of digital design, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics, and knowledge of design validation methodologies are commonly expected. Strong problem-solving abilities, effective communication skills, and self-motivation are crucial soft skills, particularly in a remote setting. These competencies ensure the engineer can deliver high-quality work, collaborate virtually with cross-functional teams, and meet project milestones in a distributed environment.

What are some typical challenges faced by work from home RTL design engineers, and how do companies support remote collaboration?

Remote RTL Design Engineers may face challenges such as limited access to on-site lab hardware, dependence on remote computing resources, and the need for clear communication across time zones. To address these, many companies provide secure VPN access, cloud-based EDA tool licenses, and regular virtual team meetings to ensure seamless project progress. You will often collaborate with verification, software, and hardware teams via video calls, shared documentation platforms, and version control systems. Structured onboarding, virtual mentorship programs, and flexible work hours are additional ways organizations support remote RTL designers. Adapting to these systems helps maintain productivity and fosters a collaborative team environment despite geographical distances.

What are popular job titles related to Work From Home Rtl Design Engineer jobs in Oregon?

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Work From Home Rtl Design Engineer jobs near you

Principal ASIC Physical Design Engineer

K2 Space

OR • On-site, Remote

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 26 days ago

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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