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Work From Home Dft Engineer Jobs (NOW HIRING)

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

K2 Space

Senior DFT Engineer

$170K - $250K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... Strong communication skills and the ability to work independently with minimal ramp-up.

Next Step Systems

FPGA Engineer - Work From Home

Chicago, IL · On-site +1

$133K - $172K/yr

FPGA Engineer - Work From Home We are seeking a talented and self-motivated FPGA Engineer to join a growing hardware engineering team. Our culture emphasizes teamwork and focuses on continuous ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

AO Globe Life

Work From Home

Virginia Beach, VA · On-site +1

Join our fully virtual, work-from-home team where you can earn an exceptional income while still cherishing every precious moment with your loved ones. With the freedom to set your own hours, you can ...

The Jernigan Agency

WORK FROM HOME

Arlington, TX · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

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Work From Home Dft Engineer information

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$73K

$129.5K

$249K

How much do work from home dft engineer jobs pay per year?

As of Aug 5, 2026, the average yearly pay for work from home dft engineer in the United States is $129,511.00, according to ZipRecruiter salary data. Most workers in this role earn between $103,000.00 and $134,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a work from home DFT engineer?

To thrive as a Work From Home Dft Engineer, you need a solid background in digital logic design, verification methodologies, and a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Mentor, or Cadence for Design-for-Test (DFT) implementation, along with expertise in scripting languages such as TCL and Python, is highly valuable. Strong problem-solving skills, proactive communication, and the ability to work independently are essential soft skills in a remote setting. These competencies enable efficient test strategy development, seamless collaboration with distributed teams, and high-quality deliverables in a dynamic virtual environment.

What are the main challenges faced by work from home DFT engineers and how can they be addressed?

A key challenge for Work From Home Dft Engineers is maintaining effective communication and collaboration with team members who may be in different locations or time zones. To address this, engineers often rely on regular virtual meetings, cloud-based collaboration tools, and thorough documentation to stay aligned on project goals and progress. Another challenge can be accessing secure lab resources or hardware remotely, which requires familiarity with remote access protocols and careful coordination with IT teams. By proactively managing these aspects, remote DFT engineers can ensure productivity and maintain strong connections with cross-functional teams, ultimately contributing to project success.

What is a work from home DFT engineer?

A Work From Home DFT (Design for Test) Engineer is responsible for developing and implementing test methodologies to ensure the manufacturability and reliability of semiconductor designs, all while working remotely. They create scan chains, ATPG (Automatic Test Pattern Generation), and BIST (Built-In Self-Test) techniques to enhance chip testability. This role requires strong knowledge of digital design, test architectures, and scripting languages. Remote DFT engineers collaborate with design and verification teams using online communication and project management tools to meet testing requirements.

More about Work From Home Dft Engineer jobs
What cities are hiring for Work From Home Dft Engineer jobs? Cities with the most Work From Home Dft Engineer job openings:
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Work From Home Dft Engineer jobs near you
Infographic showing various Work From Home Dft Engineer job openings in the United States as of July 2026, with employment types broken down into 50% Full Time, 25% Part Time, and 25% Contract. Highlights an 100% Remote job distribution, with an average salary of $129,511 per year, or $62.3 per hour.

DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 7 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
 
Year of Exp: 8+ yrs to 15 yrs.
 
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.