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Vice President Asic Design Engineer Jobs (NOW HIRING)

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

Credo, Inc

Principal ASIC Design Engineer

San Jose, CA · On-site

$180K - $210K/yr

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Atom Computing

Principal ASIC Design Engineer

Boulder, CO · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...

Atom Computing

Principal ASIC Design Engineer

Boulder, CO · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Cisco

ASIC Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Experience with ASIC design flows including simulation, synthesis, and static timing analysis ... Proficiency in engineering scripting and automation (Python, Perl, TCL, shell). * Experience with ...

Atom Computing

Principal ASIC Design Engineer

Austin, TX · On-site

$180K - $220K/yr

... engineering, specifically in ASIC/SoC environments. Qualifications * Have gone through 2 or more complete ASIC design cycles. * Experience porting designs from FPGA prototypes to ASICs * Proficiency ...

Infoyogi LLC

ASIC/RTL Design Engineer

San Jose, CA

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...

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How much do vice president asic design engineer jobs pay per year?

As of Jun 10, 2026, the average yearly pay for vice president asic design engineer in the United States is $157,532.00, according to ZipRecruiter salary data. Most workers in this role earn between $115,000.00 and $190,000.00 per year, depending on experience, location, and employer.

What does a Vice President ASIC Design Engineer do?

A Vice President ASIC Design Engineer leads teams in designing and developing Application-Specific Integrated Circuits (ASICs) for various electronic products. This role involves managing engineering teams, setting technical strategy, overseeing project timelines, and ensuring the quality and efficiency of ASIC development. They also collaborate with other departments, such as product management and manufacturing, to deliver chip solutions that meet business and customer needs. Strong technical expertise, leadership skills, and experience in semiconductor engineering are essential for this position.

What are the key skills and qualifications needed to thrive as a Vice President ASIC Design Engineer, and why are they important?

To thrive as a Vice President ASIC Design Engineer, you need deep expertise in digital and analog ASIC design, leadership experience, and an advanced degree in electrical engineering or a related field. Proficiency with industry-standard EDA tools (such as Cadence, Synopsys, or Mentor Graphics), knowledge of verification methodologies, and familiarity with semiconductor manufacturing processes are essential. Outstanding strategic thinking, communication, and team management abilities distinguish top performers in this leadership role. These competencies are crucial for driving innovation, ensuring high-quality chip design, and leading multidisciplinary engineering teams to successful project delivery.

How does a Vice President ASIC Design Engineer typically contribute to cross-functional decision-making within an organization?

A Vice President ASIC Design Engineer plays a pivotal role in cross-functional collaboration by bridging the gap between engineering, product management, and executive leadership. They are responsible for aligning ASIC design strategies with business objectives, facilitating communication between technical teams and stakeholders, and ensuring that design decisions support overall company goals. This often involves participating in high-level planning meetings, setting technical direction, and providing expertise during product roadmap discussions. Their leadership ensures that projects stay on schedule, adhere to quality standards, and meet market demands.
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Vice President Asic Design Engineer jobs near you
Principal ASIC Design Engineer

Principal ASIC Design Engineer

Credo, Inc

San Jose, CA

$180K - $210K/yr

Full-time

Posted 28 days ago

Job description

Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers.


Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure.


At Credo, you'll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what's possible for some of the world's most important companies. Our portfolio includes cutting edge solutions including our software,optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables(AECs) all designed for maximum performance, energy efficiency, and scalability.


We foster a culture oftechnical excellence, collaboration, and continuous learning, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale.


Join us and help us architect the next generation of disruptive networking technologies - because at Credo, We Connect.


About the Role

As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.


Responsibilities

  • Design, implement, and debug complex logic blocks.
  • Integrate complex IPs from internal and external vendors.
  • Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
  • Participate in design and code reviews to ensure quality.
  • Develop functional tests/testbenches and run RTL and gate-level simulations.
  • Work with verification, DFT, and physical design engineers to achieve successful tape-outs.
  • Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams.


Basic Qualifications

  • BS/MS degree in Electrical Engineering or Computer Science.
  • 10+ years of relevant ASIC design experience.
  • Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
  • Proficiency in Verilog/SystemVerilog RTL design.
  • Knowledge of synthesis and static timing analysis.
  • Experience developing testbenches and test cases; familiarity with UVM.
  • Experience with gate-level simulations, chip bring-up, and validation.
  • Proven track record of successful production tape-outs.


Preferred Qualifications

  • Expertise in scripting languages (Python, Tcl, Perl, Shell).
  • Familiarity with DFT methodology and physical design flow.
  • Hands-on experience with STA and timing closure.
  • Strong problem-solving and planning skills.
  • Excellent communication and collaboration abilities.


The base salary range for this position is $180,000 - $210,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.


Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.


If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.

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