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Temp Physical Design Engineer Jobs (NOW HIRING)

Physical Design Engineer

Sunnyvale, CA ยท On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Physical Design Engineer

Austin, TX ยท On-site

$150 - $200/hr

We're looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in ...

Physical Design Engineer

San Jose, CA ยท On-site

$159K - $164K/yr

Job Title- Physical Design Engineer Location - San Jose, CA (Onsite) Duration - 6+ months * Good understanding of Cadence tools (Innovous, Quantus, Voltus). * Deep knowledge about industry standards ...

$140K - $156K/yr

The Physical Design Engineer willbe an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edgelow powerAISoC ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

Cupertino, CA ยท On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Physical Design Engineer

San Jose, CA ยท On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Physical Design Engineer

Beaverton, OR ยท On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

Cupertino, CA ยท On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

Beaverton, OR ยท On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

San Jose, CA ยท On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

Physical Design Engineer

Beaverton, OR ยท On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer

Cupertino, CA ยท On-site

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Physical Design Engineer

San Jose, CA ยท On-site

$150 - $200/hr

Physical Design Engineer** to join our Silicon Engineering and Physical Design organization. In this role, you will be responsible for implementing advanced custom IP and SoC designs from RTL through ...

Physical Design Engineer

San Francisco, CA ยท On-site

$160K - $164K/yr

Job Title: Physical Design Engineer Location: San Francisco, CA (Bay Area) * Good understanding of Cadence tools (Innovous, Quantus, Voltus). (Must) * Deep knowledge about industry standards in ...

Physical Design Engineer

Cupertino, CA ยท On-site

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

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Temp Physical Design Engineer information

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$95K

$141.5K

How much do temp physical design engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for temp physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

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Physical Design Engineer

Sunnyvale, CA โ€ข On-site

$159K - $164K/yr

Contractor

Re-posted 12 days ago


Job description


Job Title: Physical Design Engineer 
Location:Sunnyvale, CA OR Austin,TX
Duration: Long term
experience: 5–18 years only (
No 18+ years profile)

Job Overview:
We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning.
Key Responsibilities:
Block-Level Physical Design:
• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure – Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure – Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.
Top-Level Physical Design:
• Chip-Level Floorplanning & Hierarchical Design – Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution – Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks – Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off – Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
• DFT Integration – Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.
 
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