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Tapeout Design Engineer Jobs in California (NOW HIRING)

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

OmniVision Technologies

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Full-chip integration and verification for tapeout. Annual base salary for this role in California ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Astera Labs

Tech Lead Design Engineer

San Jose, CA · On-site

$185K - $240K/yr

Drive structured, data-driven design decisions in support of aggressive tapeout schedules Basic Qualifications * Bachelor's degree in Electrical Engineering, Computer Engineering, or related field ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Will work of full project lifecycle from inception to tapeout. Qualifications: * BSEE with 5+ years ...

Lumilens

Sr. Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard ... Engineering, or a related field. * Experience: 8+ years of hands-on physical design experience ...

Nokia

Senior Analog EDA/CAD ASIC Engineer

Sunnyvale, CA · On-site

$120K - $171K/yr

High-Speed Analog EDA/CAD Engineer: Brief Description: Full-time position. Infinera is seeking an ... Execute and support layout efforts including archive and tapeout processes Minimum Expertise ...

Ametek

Analog and Mixed Signal Design Engineer

Pasadena, CA · On-site

$212K/yr

Oversee tapeout and fabrication activities to ensure design readiness and successful execution. * Work with test engineering teams to develop test hardware and test plans. * Support chip bring-up ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA · On-site

Tapeout + productization experience STA Engineer * SoC-level timing analysis & closure * PrimeTime, Tempus, or similar Physical Design Engineer * Floorplanning, CTS, routing, signoff * Timing ...

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Tapeout Design Engineer information

What is a tapeout design engineer?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What are the key skills and qualifications needed to thrive as a tapeout design engineer?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are some common challenges tapeout design engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

What are popular job titles related to Tapeout Design Engineer jobs in California?

For Tapeout Design Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Tapeout Design Engineer jobs in California look for?

The top searched job categories for Tapeout Design Engineer jobs in California are:

What cities in California are hiring for Tapeout Design Engineer jobs?

Cities in California with the most Tapeout Design Engineer job openings:

Tapeout Design Engineer jobs near you
Infographic showing various Tapeout Design Engineer job openings in California as of August 2026, with employment types broken down into 88% Full Time, 10% Part Time, and 2% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Principal Physical Design Engineer

Celero Communications, Inc.

San Jose, CA

$150K - $250K/yr

Full-time

Re-posted 16 days ago

Job description

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world's most advanced AI and data center infrastructure.

We are seeking an experienced Physical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Locations: San Jose, CA (preferred) or Irvine, CA (HQ)

Core Responsibilities
RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness. 

Key Qualifications
Must have 5+ years of relevant ASIC physical design experience (depending on degree level).
Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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