Design Engineer, Verification
$86K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $86,000.00 - $184,000.00 The ...
$86K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $86,000.00 - $184,000.00 The ...
$86K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $86,000.00 - $184,000.00 The ...
Austin, TX · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Austin, TX · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Austin, TX · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Austin, TX · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Austin, TX · On-site
$86K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $86,000.00 - $184,000.00 The ...
Austin, TX · On-site
$86K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $86,000.00 - $184,000.00 The ...
Santa Clara, CA · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Santa Clara, CA · On-site
$106K - $205K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $205,000.00 The ...
Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development ... Your proven experience mentoring junior engineers and interns is a significant advantage. * A solid ...
Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development ... Your proven experience mentoring junior engineers and interns is a significant advantage. * A solid ...
Richardson, TX · On-site
$106K - $296K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $296,000.00 The ...
Richardson, TX · On-site
$106K - $296K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $296,000.00 The ...
Austin, TX · On-site
$106K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $184,000.00 The ...
Austin, TX · On-site
$106K - $184K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $184,000.00 The ...
Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development ... Your proven experience mentoring junior engineers and interns is a significant advantage. * A solid ...
Verilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development ... Your proven experience mentoring junior engineers and interns is a significant advantage. * A solid ...
It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ... Internship will be based in San Jose location. Ideal candidates should be from local school near ...
It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ... Internship will be based in San Jose location. Ideal candidates should be from local school near ...
Austin, TX · On-site
$72K - $148K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Prior related internship or co-op experience * Demonstrated prior leadership experience in the ...
Austin, TX · On-site
$72K - $148K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Prior related internship or co-op experience * Demonstrated prior leadership experience in the ...
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Prior related internship or co-op experience * Demonstrated prior leadership experience in the ...
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Prior related internship or co-op experience * Demonstrated prior leadership experience in the ...
Austin, TX · On-site
$106K - $296K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $296,000.00 The ...
Austin, TX · On-site
$106K - $296K/yr
... as Verilog/System-Verilog. * Candidate should have good background/knowledge of typical IP ... Ability to guide and mentor interns as needed. Expected Salary Range $106,000.00 - $296,000.00 The ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
Milpitas, CA · On-site
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
Milpitas, CA · On-site
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
Prior internship or undergraduate research experience is highly desired. Preferred Qualifications ... Experience with FPGA firmware development using VHDL, Verilog, or System Verilog to model, design ...
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
$117K - $200K/yr
Proficiency with Hardware description language such as VHDL, Verilog or System Verilog ... Interns are eligible for some of the benefits listed. Our pay ranges are determined by role, level ...
Phoenix, AZ · On-site
$164K - $311K/yr
... internship experiences. Minimum Qualifications: Bachelor's degree in Computer Engineering ... Hands-on experience with hardware modeling languages, including System Verilog or Verilog.
Phoenix, AZ · On-site
$164K - $311K/yr
... internship experiences. Minimum Qualifications: Bachelor's degree in Computer Engineering ... Hands-on experience with hardware modeling languages, including System Verilog or Verilog.
$8.65 - $9.86
2% of jobs
$9.86 - $11.06
4% of jobs
$11.06 - $12.26
14% of jobs
$12.72 is the 25th percentile. Wages below this are outliers.
$12.26 - $13.46
12% of jobs
$13.46 - $14.66
15% of jobs
The median wage is $14.84 / hr.
$14.66 - $15.87
18% of jobs
$17.03 is the 75th percentile. Wages above this are outliers.
$15.87 - $17.07
10% of jobs
$17.07 - $18.27
6% of jobs
$18.27 - $19.47
8% of jobs
$19.47 - $20.67
5% of jobs
$20.67 - $21.87
5% of jobs
$8
$15
$21
| Aspect | System Verilog Internship | Hardware Design Engineer |
|---|---|---|
| Required Credentials | Enrolled in or recent graduate of Electrical Engineering or related field | Bachelor's or Master's in Electrical Engineering, VLSI, or related |
| Work Environment | Internship programs in tech companies, labs, or research institutions | Full-time professional roles in hardware design teams |
| Industry Usage | Entry-level, training-focused, project-based | Design, development, and testing of hardware components |
| Common Search/Comparison | Yes | Yes |
The System Verilog Internship provides hands-on experience in hardware description languages for students or recent graduates, focusing on learning and skill development. In contrast, a Hardware Design Engineer is a full-time professional responsible for designing and implementing hardware systems. Both roles are related to hardware development but differ in experience level, responsibilities, and career stage.

$86K - $184K/yr
Full-time
Posted 19 days ago
8.3
Based on 35 frontline employees who took The Breakroom Quiz
68th of 535 rated manufacturers
About GlobalFoundries
GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GF makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Summary of Role:
This role is for those individuals who after graduating have worked in the area of design verification/performance/modeling and are interested to build a career in the area of hardware design verification. An ideal candidate would be required to perform various duties associated in the art of design & design verification, performance and modeling by utilizing modern tools/methodologies
Primary/Essential Responsibilities:
Job requires individual to perform various tasks associated with Design Verification RISCV architecture Processors/Cores
These tasks include but not limited to
Reviewing Design and RISCV Standard Specifications,
Test Bench Development, Test Plan Creation, Tests Creation, Test Case Debug, Coverage Closure.
Modeling, Flow and Methodology development
Other Responsibilities:
Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
Required/Essential Qualifications:
Education - Graduates in Electrical, Electronics and/or Computer Engineering major or a related field with Computer architecture and VLSI Design as an important and primary part of the curriculum.
Must have at least an overall 3.0 GPA.
Experience - Bachelor's, with 3 to 5 years of experience or Master's degree holders with 1 to 3 years of experience. Experience should be relevant/recent and appropriate.
Candidate should possess a good understanding of Hardware Description Languages such as Verilog/System-Verilog.
Candidate should have good background/knowledge of typical IP Development/Verification and/or SOC Development/Verification process.
Candidate is expected to possess good communication skills and an uncanny ability to document various aspects of process/methodologies.
Language Fluency - English (Written & Verbal)
Must have knowledge in UNIX OS, Assembly & C Programming. Python or Perl Scripting language.
Curiosity to learn new tools/languages
Preferred Qualifications:
Demonstrated prior leadership experience in the workplace, school projects, competitions, etc.
Project management skills, i.e., the ability to innovate and execute on solutions that matter; the ability to navigate ambiguity
Ability to guide and mentor interns as needed.
Expected Salary Range
$86,000.00 - $184,000.00The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law
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Sourced by ZipRecruiter
Manufacturing
10,000+ Employees
Malta, NY, US
2009