ZipRecruiter

Log In

1

Standard Cell Design Jobs (NOW HIRING)

Substrate

Standard Cell Design Lead

San Francisco, CA · On-site

$150K - $275K/yr

Standard Cell Design Lead Substrate is addressing one of the most important technological problems facing the United States. At the intersection of advanced manufacturing and cutting-edge physics, we ...

Nvidia

Senior Circuit Design Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

We are now hiring for a Senior Circuit Design Engineer for Standard Cell and/or ROM. NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It ...

Oklo

Hot Cell Design Engineer

Santa Clara, CA · On-site +1

Position Description: As a Hot Cell Design Engineer at Oklo, you will help shape a highly ... Knowledge of NRC and/or DOE regulatory requirements and nuclear standards for nuclear facilities

next page

Showing results 1-20

All JobsStandard Cell Design Jobs

Standard Cell Design information

See salary details

$12

$21

$30

How much do standard cell design jobs pay per hour?

As of Jul 26, 2026, the average hourly pay for standard cell design in the United States is $21.64, according to ZipRecruiter salary data. Most workers in this role earn between $16.83 and $27.16 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Standard Cell Design position, and why are they important?

To thrive in Standard Cell Design, you need a solid background in electrical or electronics engineering, semiconductor device physics, and CMOS circuit design, typically with a relevant degree. Familiarity with EDA tools like Cadence Virtuoso, Synopsys, and layout verification software, as well as knowledge of physical design rules and scripting languages (e.g., Python or TCL), is essential. Attention to detail, strong problem-solving abilities, and the ability to collaborate with multidisciplinary teams are valuable soft skills. These competencies enable you to create robust, efficient standard cells that meet performance, area, and power targets critical for advanced chip design.

What is a Standard Cell Design job?

A Standard Cell Design job involves creating and optimizing fundamental building blocks (standard cells) used in digital integrated circuits. Engineers in this role define the cell architecture, design layouts, and ensure timing, power, and area efficiency. They work closely with circuit and physical design teams to deliver high-quality libraries for ASIC and SoC development. Strong skills in CMOS design, EDA tools, and scripting are essential for success in this field.

What are some typical challenges faced in a Standard Cell Design role?

Professionals in Standard Cell Design often encounter challenges related to meeting aggressive performance, power, and area (PPA) targets while adhering to strict design rules and technology constraints. Balancing design trade-offs, resolving design rule violations, and optimizing cells for manufacturability require both technical expertise and creative problem-solving skills. Collaboration with process engineers, verification teams, and EDA tool specialists is common to address issues that arise throughout the design flow. Successfully navigating these challenges improves both the quality and yield of integrated circuits, making this role both vital and intellectually rewarding in semiconductor development.

More about Standard Cell Design jobs
What cities are hiring for Standard Cell Design jobs? Cities with the most Standard Cell Design job openings:
What are the most commonly searched types of Standard Cell Design jobs? The most popular types of Standard Cell Design jobs are:
What job categories do people searching Standard Cell Design jobs look for? The top searched job categories for Standard Cell Design jobs are:
Standard Cell Design jobs near you
Infographic showing various Standard Cell Design job openings in the United States as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $45,021 per year, or $21.6 per hour.
Standard Cell Design Lead

Standard Cell Design Lead

Substrate

San Francisco, CA • On-site

$150K - $275K/yr

Full-time

Posted 29 days ago

Job description

Standard Cell Design Lead
Substrate is addressing one of the most important technological problems facing the United States. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen America's technological leadership. We are a team of world-class scientists, engineers, and technical experts building technology for the United States.
Summary
As a Standard Cell Design Lead, you will develop and optimize standard cell libraries while leading cell characterization and library validation efforts. This role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. You will work across multiple locations including external fabrication facilities. This is a full-time, onsite position.
Responsibilities
  • Lead standard cell library development including logic gates, flip-flops, and complex cells
  • Optimize cell layouts for power, performance and area across Vth's and drive strengths
  • Characterize cell library including timing, power, and noise analysis for library models
  • Develop Liberty (.lib) timing files and LEF physical abstractions for EDA tool integration
  • Collaborate with PDK and process teams to ensure cell performance meets targets
  • Implement DFM techniques and validate cells against DRC/LVS rules
  • Support all DFT fault models including cell aware, physical aware, stuck-at and transition
  • Optimize cell architectural requirements including multi-Vt and multi-channel options
  • Lead library validation and qualification across distributed design and fabrication teams

Required Qualifications
  • 10+ years experience in standard cell design, library development and characterization
  • Deep understanding of standard cell architecture, layout, and optimization strategies
  • Strong background in cell characterization and Liberty timing model generation
  • Experience with layout tools (Cadence Virtuoso, Synopsys Custom Compiler, or similar)
  • Proficiency with characterization tools and SPICE simulation for timing/power analysis
  • Proven ability to balance area, performance, and power trade-offs in cell design

Preferred Qualifications
  • Advanced degree in Electrical Engineering or related field
  • Experience with advanced node standard cells or FinFET/GAA library development
  • Background in low-power design techniques and multi-threshold voltage libraries
  • Familiarity with EDA flows and library integration requirements
  • Experience in research-driven or startup semiconductor environments

Salary Range
$150,000-$275,000 USD
Substrate is an equal opportunity employer. It provides equal employment opportunity to all applicants without regard to race, color, religion, national origin, disability, medical condition, marital status, sex, gender, age, military or veteran status, or any other characteristic protected by applicable federal, state, or local laws.
Substrate will provide reasonable accommodations to applicants with disabilities. If you need an accommodation during the hiring process, please let your recruiter know.
Applicants must be legally authorized to work in the United States. This position is not eligible for visa sponsorship.

Apply