ZipRecruiter

Log In

1

Standard Cell Design Jobs (NOW HIRING)

Trispark Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$161.80K - $166.60K/yr

... standard cell placement, legalization, and optimization to improve area, power, and timing. • Clock Tree Synthesis (CTS) - Design and optimize low-skew, high-performance clock networks. • Routing ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159.60K - $164.30K/yr

... standard cell placement, legalization, and optimization to improve area, power, and timing. • Clock Tree Synthesis (CTS) - Design and optimize low-skew, high-performance clock networks. • Routing ...

Tanisha Systems, Inc.

Physical Design Engineer

Austin, TX · On-site

$134.80K - $138.70K/yr

Placement & Optimization - Perform standard cell placement, legalization, and optimization to improve area, power, and timing. * Clock Tree Synthesis (CTS) - Design and optimize low-skew, high ...

Apple

GPU Physical Design PPA Engineer

Austin, TX

$134.80K - $138.80K/yr

... and drive standard cell and memory hard-IP offerings and recommend usage/methodology to the ... Proficiency in logic design principles, physical design, power and timing concepts. Knowledge of ...

Apple

GPU Physical Design PPA Engineer

Austin, TX · On-site

$134.80K - $138.80K/yr

... and drive standard cell and memory hard-IP offerings and recommend usage/methodology to the ... Experience with industry standard physical design tools.Experience with one or more of the ...

Trispark Inc

Physical Design Engineer

Austin, TX · On-site

$134.80K - $138.70K/yr

... standard cell placement, legalization, and optimization to improve area, power, and timing. • Clock Tree Synthesis (CTS) - Design and optimize low-skew, high-performance clock networks. • Routing ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

Intel

Senior CPU Physical Design Engineer

Austin, TX

$134.80K - $138.80K/yr

Qualify and validate new PDK versions, standard cell libraries using backend design environment for RTL2GDS (Synthesis & APR) and custom verification flows. * Conduct verification and signoff ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156.85K - $160K/yr

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

Broadcom

IC Design Engineer

Irvine, CA · On-site

$108K - $192K/yr

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically ...

Broadcom

IC Design Engineer

San Jose, CA · On-site

$108K - $192K/yr

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156.85K - $160K/yr

Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks. * Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal ...

Broadcom

IC Design Engineer

San Jose, CA · On-site

$108K - $192K/yr

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically ...

next page

Showing results 1-20

People also search for

All JobsStandard Cell Design Jobs

Standard Cell Design information

See salary details

$12

$21

$30

How much do standard cell design jobs pay per hour?

As of Jun 3, 2026, the average hourly pay for standard cell design in the United States is $21.64, according to ZipRecruiter salary data. Most workers in this role earn between $16.83 and $27.16 per hour, depending on experience, location, and employer.

What is a Standard Cell Design job?

A Standard Cell Design job involves creating and optimizing fundamental building blocks (standard cells) used in digital integrated circuits. Engineers in this role define the cell architecture, design layouts, and ensure timing, power, and area efficiency. They work closely with circuit and physical design teams to deliver high-quality libraries for ASIC and SoC development. Strong skills in CMOS design, EDA tools, and scripting are essential for success in this field.

What are the key skills and qualifications needed to thrive in the Standard Cell Design position, and why are they important?

To thrive in Standard Cell Design, you need a solid background in electrical or electronics engineering, semiconductor device physics, and CMOS circuit design, typically with a relevant degree. Familiarity with EDA tools like Cadence Virtuoso, Synopsys, and layout verification software, as well as knowledge of physical design rules and scripting languages (e.g., Python or TCL), is essential. Attention to detail, strong problem-solving abilities, and the ability to collaborate with multidisciplinary teams are valuable soft skills. These competencies enable you to create robust, efficient standard cells that meet performance, area, and power targets critical for advanced chip design.

What are some typical challenges faced in a Standard Cell Design role?

Professionals in Standard Cell Design often encounter challenges related to meeting aggressive performance, power, and area (PPA) targets while adhering to strict design rules and technology constraints. Balancing design trade-offs, resolving design rule violations, and optimizing cells for manufacturability require both technical expertise and creative problem-solving skills. Collaboration with process engineers, verification teams, and EDA tool specialists is common to address issues that arise throughout the design flow. Successfully navigating these challenges improves both the quality and yield of integrated circuits, making this role both vital and intellectually rewarding in semiconductor development.
More about Standard Cell Design jobs
What cities are hiring for Standard Cell Design jobs? Cities with the most Standard Cell Design job openings:
What are the most commonly searched types of Standard Cell Design jobs? The most popular types of Standard Cell Design jobs are:
What job categories do people searching Standard Cell Design jobs look for? The top searched job categories for Standard Cell Design jobs are:
Standard Cell Design jobs near you
Principal Engineer, Design Technology Co-optimization

Principal Engineer, Design Technology Co-optimization

Intel

Austin, TX

Full-time

Medical, Retirement, PTO

Posted 18 hours ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 139 rated electronics manufacturers

Job description

Job Details:Job Description: 

Organization Description

Advanced Design & Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tie0/tie1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis is conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost.
Job Role & Responsibility Description
As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs. You will directly interface with key Intel foundry customers to understand technology and library gaps and drive co-optimization with Intel foundry technology development teams and EDA partners. Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area, collaborating with EDA partners to optimize cell content in standard cell library to improve Intel technology entitlement at product level.

Required Skills and Experience

  • Strong technical understanding of advanced semiconductor technology
  • Strong technical understanding of foundation IP design and design-technology co-optimization
  • Experience in standard cell library design with good understanding of MOSFET electrical characteristics, local layout effects, variability at advanced nodes
  • Experience with library cell characterization methodology and tools and Spice circuit simulations
  • Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
  • Excellent oral and written communication skills
  • Collaborative mindset and great team player
  • Good track record of technical leadership and delivery

Preferred Skills and Experience

  • Experience in product designs with good understanding of signoff methodology, tradeoffs across power, performance and tradeoff
  • Familiar with pre and post Si foundry benchmarking practices
  • Familiar with EDA tool design and optimization with experience in identification, design and verification of cells targeted to improve product level PPA
  • Experience in foundation IP Si validation
Qualifications:
  • Ph.D. or master's degree in electrical engineering or computer science
  • 10+ years of industry experience
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

View All Intel Jobs

Apply