Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM. * Design trade-offs between power, performance, and area (PPA). * Custom digital circuit ...
Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington, MA · On-site
$148K/yr
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington, MA · On-site
$148K/yr
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
Quick apply
... and SRAM/memory interface considerations. * Strong understanding of silicon-level design ... constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and ...
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
... Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in ... What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL ...
... Access Memory (SRAM) memory compilers. This team hires some of the biggest problem solvers in ... What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL ...
Circuit Design Automation Engineer
$172K - $305K/yr
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
Circuit Design Automation Engineer
$172K - $305K/yr
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
Circuit Design Automation Engineer
$172K - $305K/yr
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
Circuit Design Automation Engineer
$172K - $305K/yr
... memory compiler technologies to facilitate in creating memory arrays in large SoC designs - Debug ... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ...
SRAM Mask Layout Designer
Austin, TX · On-site
Are you interested in joining Qualcomm's High-performance CPU Team as a SRAM Mask Layout Designer ... the circuit design engineers. * Work independently and execute memory layout with little ...
SRAM Mask Layout Designer
Austin, TX · On-site
Are you interested in joining Qualcomm's High-performance CPU Team as a SRAM Mask Layout Designer ... the circuit design engineers. * Work independently and execute memory layout with little ...
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
Quick apply
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
Distinguished Engineer, Digital ASIC
Burlington, MA · On-site +1
$148K/yr
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
Distinguished Engineer, Digital ASIC
Burlington, MA · On-site +1
$148K/yr
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
You'll characterize cutting-edge memory circuits (SRAM, Flash, EEPROM, eFuse) on advanced ... Your silicon feedback shapes design decisions and qualifies innovative IP for cutting-edge products ...
You'll characterize cutting-edge memory circuits (SRAM, Flash, EEPROM, eFuse) on advanced ... Your silicon feedback shapes design decisions and qualifies innovative IP for cutting-edge products ...
Knowledge of memory design and architecture, including Static Random-Access Memory (SRAM) and Flash memory * In-depth knowledge of semiconductor manufacturing processes, including fabrication ...
Knowledge of memory design and architecture, including Static Random-Access Memory (SRAM) and Flash memory * In-depth knowledge of semiconductor manufacturing processes, including fabrication ...
Knowledge of memory design and architecture, including Static Random-Access Memory (SRAM) and Flash memory * In-depth knowledge of semiconductor manufacturing processes, including fabrication ...
Knowledge of memory design and architecture, including Static Random-Access Memory (SRAM) and Flash memory * In-depth knowledge of semiconductor manufacturing processes, including fabrication ...
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, CA · On-site
On-chip tightly coupled SRAM & L3 cache controller architecture/design * Experience with x86 or ARM CPU/bus architectures * Ordering of memory transactions and methods to enforce proper ordering in ...
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
San Diego, CA · On-site
On-chip tightly coupled SRAM & L3 cache controller architecture/design * Experience with x86 or ARM CPU/bus architectures * Ordering of memory transactions and methods to enforce proper ordering in ...
Distinguished Engineer, ASIC (CONTRACT)
Burlington, MA · On-site +1
$180K/yr
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
Distinguished Engineer, ASIC (CONTRACT)
Burlington, MA · On-site +1
$180K/yr
Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design. * Prior work at advanced ...
Sram Memory Design information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do sram memory design jobs pay per hour?
As of Jun 29, 2026, the average hourly pay for sram memory design in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.
What is the difference between Sram Memory Design vs DRAM Memory Design?
| Aspect | Sram Memory Design | DRAM Memory Design |
|---|---|---|
| Focus | Designing static RAM cells, optimizing speed and power | Designing dynamic RAM cells, focusing on density and refresh management |
| Work Environment | Semiconductor companies, hardware design labs | Memory chip manufacturers, integrated circuit design teams |
| Credentials | Electrical engineering, specialized in digital and memory design | Electrical engineering, with emphasis on memory architectures |
Sram Memory Design and DRAM Memory Design both involve memory chip development but differ in cell technology and application focus. Sram is faster and used for cache memory, while DRAM offers higher density for main memory. Understanding these differences helps in choosing the right design approach for specific hardware needs.
What is SRAM memory design?
SRAM memory design refers to the process of creating Static Random Access Memory (SRAM) circuits used in electronic devices for fast, temporary data storage. Designers focus on optimizing speed, power consumption, and area while ensuring data stability and reliability. The process involves schematic design, layout, verification, and testing of SRAM cells and arrays to meet specific performance requirements. SRAM is commonly used in cache memory and other high-speed applications because it retains data as long as power is supplied, without needing to be refreshed like DRAM.
What are some common challenges faced by engineers in SRAM Memory Design and how can they be addressed?
Engineers in SRAM Memory Design often encounter challenges such as optimizing for low power consumption while maintaining high performance and ensuring data integrity under various process, voltage, and temperature variations. Addressing these challenges requires close collaboration with process technology teams, rigorous simulation and verification, and frequent design reviews. Additionally, balancing area efficiency with speed can be complex, so ongoing learning and teamwork are essential for success in this role.
What are the key skills and qualifications needed to thrive as an SRAM Memory Design Engineer, and why are they important?
To thrive as an SRAM Memory Design Engineer, you need a strong background in electrical engineering, semiconductor physics, and circuit design, often supported by a relevant degree. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, along with knowledge of industry standards, is typically required. Analytical thinking, attention to detail, and effective teamwork are crucial soft skills in this role. These competencies are essential for designing reliable, high-performance memory circuits that meet stringent requirements for speed, power, and manufacturability.
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Key responsibilities
Conduct memory pathfinding activities and optimize power, performance, and area through design technology co-optimization and product design enablement.
Perform memory bit-cell and complex periphery IC layout and automation.
Design memory arrays and IP, drive memory circuit innovation, and execute test-chip design.
Intel rating
8.7
Based on 144 frontline employees who took The Breakroom Quiz
10th of 139 rated electronics manufacturers
Job description
Job Details:Job Description:
The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.
The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.
You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:
- Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
- Memory bit-cell and complex periphery IC layout and automation.
- Memory array/IP design, memory circuit innovation, test-chip design.
- Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:
- Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
- Design trade-offs between power, performance, and area (PPA).
- Custom digital circuit design, simulation, layout design, and verification.
- Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications:
- PhD with 1-2 years of professional experience gained through either internships or full-time employment.
- Design technology co-optimization (DTCO).
- Post-Si validation experience.
- Knowledge of the CMOS ASIC design flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968