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Sram Design Engineer Jobs (NOW HIRING)

Micron

DRAM Design Engineer

Boise, ID · On-site

Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...

Micron Technology

DRAM Design Engineer

Boise, ID · On-site

Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...

Ampere Computing LLC

Circuit Design Engineer

Durham, NC · On-site

$147K - $220K/yr

You will work on transistor-level design for SRAM arrays/caches, register files, and/or custom ... Electrical or Computer Engineering - Bachelor's degree & 5 years of related experience; or MS ...

Intel

Memory Circuit Design Engineer

Austin, TX · On-site

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

Intel

Memory Circuit Design Engineer

Phoenix, AZ

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

Intel

Memory Circuit Design Engineer

Santa Clara, CA

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA

$150K - $250K/yr

We are looking for FPGA Design Engineers to develop, implement, and verify FPGA firmware for ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

E-Space

FPGA Design Engineer - Avionics

Saratoga, CA · On-site

$150K - $250K/yr

We are looking for FPGA Design Engineers to develop, implement, and verify FPGA firmware for ... Experience with a variety of FPGA platforms and vendor toolchains (e.g., flash-based, SRAM-based ...

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Sram Design Engineer information

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How much do sram design engineer jobs pay per hour?

As of Jul 19, 2026, the average hourly pay for sram design engineer in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Sram Design Engineer position, and why are they important?

To thrive as a Sram Design Engineer, a strong background in electrical engineering, VLSI design, and semiconductor device physics—often supported by a relevant bachelor’s or master’s degree—is essential. Expertise in industry-standard EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as experience with HDL languages such as Verilog or VHDL, is typically required. Attention to detail, problem-solving skills, and the ability to communicate effectively with cross-functional teams are important soft skills for the role. These skills ensure high-quality SRAM design, efficient collaboration, and the ability to meet both performance and reliability targets in advanced integrated circuits.

What are the typical daily responsibilities of a Sram Design Engineer?

As a Sram Design Engineer, your daily tasks often include designing and verifying static random-access memory (SRAM) circuits, running simulations to validate performance, and troubleshooting design issues. You’ll collaborate closely with layout engineers, verification teams, and other design engineers to optimize memory architectures and ensure compliance with power, area, and timing specifications. Additionally, you may attend design reviews, document design methodologies, and interact with foundries during tape-out or silicon validation phases. This role frequently involves both independent technical work and teamwork within a multidisciplinary environment focused on delivering high-performance semiconductor products.

What is an SRAM Design Engineer job?

An SRAM Design Engineer is responsible for designing Static Random-Access Memory (SRAM) circuits used in semiconductor chips. They focus on optimizing performance, power consumption, and area efficiency while ensuring reliable functionality. Their work includes transistor-level design, layout, simulation, and verification of SRAM cells, sense amplifiers, and peripheral circuits. They collaborate with process engineers and digital designers to integrate SRAM into larger systems. Strong knowledge of VLSI design, circuit theory, and semiconductor technology is essential for this role.

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Sram Design Engineer jobs near you
Infographic showing various Sram Design Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $105,435 per year, or $50.7 per hour.
Principal Design Engineer

Principal Design Engineer

Cadence Design Systems, Inc.

San Jose, CA • On-site

$136K - $253K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 24 days ago

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
The Cadence Advantage
  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Job Responsibility
Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.
  • Lead a team to implement SOCs or sub system chips
  • Work on RTL synthesis and floor planning
  • Build clock trees and perform optimizations
  • Close timing, IR drop and physical verification
  • Review and Document designs for taping out
  • Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:
  • BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum 1 years of experience
  • Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
  • Experience with advanced technologies like 5nm, 3ns and 2nm nodes
  • Experience using Linux servers, Script development using Shell/Perl/TCL
  • Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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