... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Circuit Design Automation Engineer
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Circuit Design Automation Engineer
$172.10K - $305.60K/yr
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Staff Engineer, SRAM Layout
San Jose, CA · On-site
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Quick apply
Design and optimize SRAM layouts at the cell, array, and peripheral levels for area, speed, power ... Lead layout reviews, mentor junior engineers, and drive best practices, optimization techniques ...
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
... Engineering, Microelectronics, or related fields * 10+ years of hands-on SRAM memory compiler ... Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ...
... Engineering, Microelectronics, or related fields * 10+ years of hands-on SRAM memory compiler ... Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ...
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$147.40K - $272.10K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
Hardware Design Engineer
Calabasas, CA · On-site
$114.62K - $191.03K/yr
As a Hardware Design Engineer, you will contribute and drive the design, development, qualification ... High density FPGAs, Network processors, DDR3/DDR4 discrete designs, SRAM, PHYs, and retimers.
Hardware Design Engineer
Calabasas, CA · On-site
$114.62K - $191.03K/yr
As a Hardware Design Engineer, you will contribute and drive the design, development, qualification ... High density FPGAs, Network processors, DDR3/DDR4 discrete designs, SRAM, PHYs, and retimers.
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Hardware Design Engineer
$114.62K - $191.03K/yr
As a Hardware Design Engineer, you will contribute and drive the design, development, qualification ... High density FPGAs, Network processors, DDR3/DDR4 discrete designs, SRAM, PHYs, and retimers.
Hardware Design Engineer
$114.62K - $191.03K/yr
As a Hardware Design Engineer, you will contribute and drive the design, development, qualification ... High density FPGAs, Network processors, DDR3/DDR4 discrete designs, SRAM, PHYs, and retimers.
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Sram Design Engineer information
See salary details
$18.03 - $23.08
1% of jobs
$23.08 - $28.13
2% of jobs
$28.13 - $33.17
7% of jobs
$33.17 - $38.22
11% of jobs
$39.68 is the 25th percentile. Wages below this are outliers.
$38.22 - $43.27
14% of jobs
$43.27 - $48.32
15% of jobs
The median wage is $48.51 / hr.
$48.32 - $53.37
14% of jobs
$53.37 - $58.41
8% of jobs
$59.90 is the 75th percentile. Wages above this are outliers.
$58.41 - $63.46
12% of jobs
$63.46 - $68.51
12% of jobs
$68.51 - $73.56
5% of jobs
$18
$50
$73
How much do sram design engineer jobs pay per hour?
As of May 31, 2026, the average hourly pay for sram design engineer in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.
What is an SRAM Design Engineer job?
An SRAM Design Engineer is responsible for designing Static Random-Access Memory (SRAM) circuits used in semiconductor chips. They focus on optimizing performance, power consumption, and area efficiency while ensuring reliable functionality. Their work includes transistor-level design, layout, simulation, and verification of SRAM cells, sense amplifiers, and peripheral circuits. They collaborate with process engineers and digital designers to integrate SRAM into larger systems. Strong knowledge of VLSI design, circuit theory, and semiconductor technology is essential for this role.
What are the key skills and qualifications needed to thrive in the Sram Design Engineer position, and why are they important?
To thrive as a Sram Design Engineer, a strong background in electrical engineering, VLSI design, and semiconductor device physics—often supported by a relevant bachelor’s or master’s degree—is essential. Expertise in industry-standard EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as experience with HDL languages such as Verilog or VHDL, is typically required. Attention to detail, problem-solving skills, and the ability to communicate effectively with cross-functional teams are important soft skills for the role. These skills ensure high-quality SRAM design, efficient collaboration, and the ability to meet both performance and reliability targets in advanced integrated circuits.
What are the typical daily responsibilities of a Sram Design Engineer?
As a Sram Design Engineer, your daily tasks often include designing and verifying static random-access memory (SRAM) circuits, running simulations to validate performance, and troubleshooting design issues. You’ll collaborate closely with layout engineers, verification teams, and other design engineers to optimize memory architectures and ensure compliance with power, area, and timing specifications. Additionally, you may attend design reviews, document design methodologies, and interact with foundries during tape-out or silicon validation phases. This role frequently involves both independent technical work and teamwork within a multidisciplinary environment focused on delivering high-performance semiconductor products.
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Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! ..Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 3+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum BS and 3+ years of relevant industry experienceExperience with microprocessor architectureExperience with logic design principles with timing and power implicationsExperience in Verilog or VHDLExperience with simulators and waveform debugging process
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction Understanding of low power microarchitecture techniques Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Experience in C or C++ programming Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976