US 2026 Hardware - Digital Intern
$35 - $45/hr
... SoC or ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr TetraMem celebrates diversity and is committed to creating an ...
$35 - $45/hr
... SoC or ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr TetraMem celebrates diversity and is committed to creating an ...
$35 - $45/hr
... SoC or ASIC development flow is a plus Team-oriented with strong communication and documentation skills Salary Range: $35-45 USD/hr TetraMem celebrates diversity and is committed to creating an ...
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Quick apply
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Exposure to ASIC or SoC design concepts * Familiarity with SystemVerilog, UVM, or Python
Chicago, IL Job Type: Intern Job Number: 24-I-01 Administration: Attorney General Bureau ... Support daily operations in a Security Operations Center (SOC), including log analysis and incident ...
Chicago, IL Job Type: Intern Job Number: 24-I-01 Administration: Attorney General Bureau ... Support daily operations in a Security Operations Center (SOC), including log analysis and incident ...
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Quick apply
San Jose, CA · On-site
Job Summary As a DFT Intern at Etched, you will help review and refine DFT flow automation to ... Exposure to ASIC or SoC design concepts * Familiarity with digital logic design fundamentals
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Conshohocken, PA · On-site
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Conshohocken, PA · On-site
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT : Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Conshohocken, PA · On-site
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Conshohocken, PA · On-site
Security Intern DEPARTMENT: Information Technology REPORTS TO: VP, Cybersecurity FLSA STATUS ... Partner with security analysts to develop and document SOC playbooks for incident response and ...
Fremont, CA · On-site
$35/hr
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We ...
Fremont, CA · On-site
$35/hr
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We ...
Summary of Duties and Responsibilities As an Information Security Assurance Associate (Intern), you ... Support daily operations in a Security Operations Center (SOC), including log analysis and incident ...
Summary of Duties and Responsibilities As an Information Security Assurance Associate (Intern), you ... Support daily operations in a Security Operations Center (SOC), including log analysis and incident ...
Rockford, IL · On-site
$400/day
Certified SS Teacher Pay (includes SLP, Soc. Work, Psych, Couns, Certified Nurse) Compensation: $40 ... Instructional Intern Compensation: $25.00/hour. Benefits: This is not a benefits-eligible position.
Rockford, IL · On-site
$400/day
Certified SS Teacher Pay (includes SLP, Soc. Work, Psych, Couns, Certified Nurse) Compensation: $40 ... Instructional Intern Compensation: $25.00/hour. Benefits: This is not a benefits-eligible position.
Job Summary Our corporate activities are growing rapidly, and we are currently seeking an Intern to ... Work directly with security analysts and engineers on active investigations and daily SOC ...
Job Summary Our corporate activities are growing rapidly, and we are currently seeking an Intern to ... Work directly with security analysts and engineers on active investigations and daily SOC ...
$8.89 - $10.29
3% of jobs
$10.29 - $11.69
3% of jobs
$11.69 - $13.09
3% of jobs
$13.09 - $14.49
9% of jobs
$14.94 is the 25th percentile. Wages below this are outliers.
$14.49 - $15.89
21% of jobs
The median wage is $16.47 / hr.
$15.89 - $17.29
26% of jobs
$18.39 is the 75th percentile. Wages above this are outliers.
$17.29 - $18.68
13% of jobs
$18.68 - $20.08
12% of jobs
$20.08 - $21.48
4% of jobs
$21.48 - $22.88
3% of jobs
$22.88 - $24.28
3% of jobs
$8
$17
$24
| Aspect | Soc Intern | Security Analyst |
|---|---|---|
| Required Credentials | Typically pursuing or holding a degree in cybersecurity, IT, or related fields | Often requires certifications like CompTIA Security+, CISSP, or CEH |
| Work Environment | Internship setting within a Security Operations Center (SOC), supervised and learning-focused | Full-time role in SOC or cybersecurity team, responsible for monitoring and incident response |
| Employer & Industry Usage | Used by organizations hiring interns to support security teams | Used by companies for ongoing security monitoring and threat management |
The main difference is that a Soc Intern is an entry-level, learning-focused position often held by students or recent graduates, while a Security Analyst is a full-time professional responsible for security monitoring, incident response, and threat analysis. Interns gain hands-on experience, whereas analysts perform ongoing security operations.

$35 - $45/hr
Other
Posted 4 days ago
About the Role
We are seeking a Digital Hardware Intern to support the design, verification, and integration of digital systems in TetraMems AI accelerators. Youll contribute to RTL design, simulations, and performance optimization for real-world AI computing applications.
Responsibilities
Support RTL design using Verilog or SystemVerilog
Assist in writing testbenches and performing functional verification
Collaborate with digital and software teams to integrate and validate system components
Contribute to timing analysis, synthesis, and performance analysis
Qualifications
Currently pursuing a degree in Electrical Engineering, Computer Engineering, or related field
Familiarity with Verilog/SystemVerilog and digital design fundamentals Exposure to simulation tools (e.g., ModelSim, VCS) and scripting (Python, Shell, or Tcl)
Understanding of SoC or ASIC development flow is a plus
Team-oriented with strong communication and documentation skills
Salary Range: $35-45 USD/hr
TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.
TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.
To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMems official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.
We encourage all interested candidates to apply through the official TetraMem Careers page.
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Computer and peripheral equipment manufacturing
11 - 50 Employees
Fremont, CA, US
2018