As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on ...
As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on ...
Staff Package Design Engineer
Austin, TX · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Staff Package Design Engineer
Austin, TX · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
We are seeking a highly skilled Flash Controller Design Engineer to contribute to the design and ... The ideal candidate will have strong experience in pre-silicon ASIC/SoC design , controller ...
We are seeking a highly skilled Flash Controller Design Engineer to contribute to the design and ... The ideal candidate will have strong experience in pre-silicon ASIC/SoC design , controller ...
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Staff Package Design Engineer
Austin, TX · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Staff Package Design Engineer
Austin, TX · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Wireless Design Engineer
San Diego, CA · On-site
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is ... As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ...
Wireless Design Engineer
San Diego, CA · On-site
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is ... As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ...
Silicon Design Verification Engineer
San Jose, CA · Hybrid
$159K - $195K/yr
This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification. THE PERSON: The candidate ...
Silicon Design Verification Engineer
San Jose, CA · Hybrid
$159K - $195K/yr
This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification. THE PERSON: The candidate ...
Principal Silicon Design Verification Engineer
Santa Clara, CA · On-site
$188K - $304K/yr
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team ... Work with cross functional teams, architecture, design, verification, partner teams for project ...
Principal Silicon Design Verification Engineer
Santa Clara, CA · On-site
$188K - $304K/yr
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team ... Work with cross functional teams, architecture, design, verification, partner teams for project ...
Silicon Design Verification Engineer, Quantum AI
Mountain View, CA · On-site
$160K - $195K/yr
Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience. * 4 years of experience in silicon design verification using SystemVerilog/UVM.
Silicon Design Verification Engineer, Quantum AI
Mountain View, CA · On-site
$160K - $195K/yr
Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience. * 4 years of experience in silicon design verification using SystemVerilog/UVM.
Wireless FPGA Prototype Design Engineer
$126K - $220K/yr
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC ... Description As a Wireless ASIC/FPGA Prototyping Design Engineer, you will work in a team developing ...
Wireless FPGA Prototype Design Engineer
$126K - $220K/yr
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC ... Description As a Wireless ASIC/FPGA Prototyping Design Engineer, you will work in a team developing ...
PLL Design Engineer
Sunnyvale, CA · On-site
$237K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...
PLL Design Engineer
Sunnyvale, CA · On-site
$237K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...
RTL Design Engineer
Irvine, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Irvine, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
Wireless FPGA Prototype Design Engineer
Bodega Bay, CA · On-site
$181K - $318K/yr
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC ... Description As a Wireless ASIC/FPGA Prototyping Design Engineer, you will work in a team developing ...
Wireless FPGA Prototype Design Engineer
Bodega Bay, CA · On-site
$181K - $318K/yr
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC ... Description As a Wireless ASIC/FPGA Prototyping Design Engineer, you will work in a team developing ...
PLL Design Engineer
Sunnyvale, CA · On-site
$237K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...
PLL Design Engineer
Sunnyvale, CA · On-site
$237K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...
RTL Design Engineer
Cupertino, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Cupertino, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Austin, TX · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Austin, TX · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
San Diego, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
San Diego, CA · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Beaverton, OR · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
RTL Design Engineer
Beaverton, OR · On-site
... Engineer ... This is an exciting position in the world class Apple mixed-signal silicon design team!..This role ...
Silicon Design Verification Engineer
Mountain View, CA · On-site
$160K - $195K/yr
About the job Be part of a team that pushes boundaries, developing custom silicon solutions that ... Debug test failures in collaboration with design engineers to ensure functionally correct digital ...
Silicon Design Verification Engineer
Mountain View, CA · On-site
$160K - $195K/yr
About the job Be part of a team that pushes boundaries, developing custom silicon solutions that ... Debug test failures in collaboration with design engineers to ensure functionally correct digital ...
Smts Silicon Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do smts silicon design engineer jobs pay per year?
What are the key skills and qualifications needed to thrive as an SMTS Silicon Design Engineer, and why are they important?
What are some common challenges faced by SMTS Silicon Design Engineers when working on complex chip architectures?
What is an SMTS Silicon Design Engineer?
Full-time
Posted 17 days ago
Google rating
8.8
Based on 92 frontline employees who took The Breakroom Quiz
31st of 186 rated software companies
Job description
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience in Verilog, SystemVerilog, or equivalent hardware description language.
- Experience with scripting for automation (e.g., shell, Python, Perl).
- Experience in one or more of the following: silicon design/verification, FPGA design/verification, or EDA tools.
Preferred qualifications:
- 1 year experience coding in one of the following programming languages including but not limited to: C, C , Python, or Java.
- Experience in one or more of the following: SoC architecture, embedded systems, firmware design.
- Experience in applying AI techniques to software or hardware development.
- Ability to start full-time role in 2026.
About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on chips powering the next generation of Google Cloud systems. You will work well both separately and as part of a team.
In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed Electronic Design Automation (EDA) tools, custom tooling, and emergent technologies from GDM and core.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target bonus equity benefits
Learn more about benefits at Google .
Responsibilities
- Collaborate in or lead projects to identify automation opportunities, analyze potential approaches, develop custom tooling or flows implementing existing first-party/third-party tools, and support deployment of the resulting solutions across global sites.
- Study, diagnose, and review technical issues by collaborating with silicon and software engineers and third-party EDA and IP vendors to analyze the sources of the issues and the impacts on user productivity.
- Develop and review code developed by other team members and users to provide feedback, ensuring best practices are followed.
- Write documents that set new technical directions. Contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
- Leverage AI to both speed the development of tools and development flows, providing more natural and higher-efficiency ways for users to interact with developed technologies.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US