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Smts Silicon Design Engineer Jobs (NOW HIRING)

Come join Apple's growing wireless silicon development team. Our wireless SOC organization is ... As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ...

PLL Design Engineer

Sunnyvale, CA · On-site

$237K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...

PLL Design Engineer

Sunnyvale, CA · On-site

$237K/yr

We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... In this highly visible role, you will drive innovation within a silicon design group with a ...

Silicon Design Verification Engineer

Mountain View, CA · On-site

$160K - $195K/yr

About the job Be part of a team that pushes boundaries, developing custom silicon solutions that ... Debug test failures in collaboration with design engineers to ensure functionally correct digital ...

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Smts Silicon Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do smts silicon design engineer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for smts silicon design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an SMTS Silicon Design Engineer, and why are they important?

To thrive as an SMTS Silicon Design Engineer, you need a deep understanding of digital and/or analog circuit design, semiconductor physics, and experience with ASIC or SoC development, usually supported by a degree in electrical or computer engineering. Proficiency in technical tools such as Verilog/VHDL, EDA tools (like Synopsys or Cadence), and simulation software, along with familiarity with industry standards, is crucial. Excellent problem-solving abilities, attention to detail, and effective teamwork and communication skills set standout engineers apart. These competencies ensure the creation of innovative, high-performance silicon solutions that meet stringent design specifications and project timelines.

What are some common challenges faced by SMTS Silicon Design Engineers when working on complex chip architectures?

SMTS Silicon Design Engineers often encounter challenges such as managing high design complexity, meeting aggressive performance and power targets, and ensuring seamless integration of multiple IP blocks. Collaborating closely with verification, software, and physical design teams is essential to address issues early and avoid costly rework. Additionally, staying current with evolving design tools and methodologies helps maintain efficiency and drive innovation in fast-paced project environments.

What is an SMTS Silicon Design Engineer?

An SMTS (Senior Member of Technical Staff) Silicon Design Engineer is a highly experienced professional responsible for designing and developing integrated circuits (ICs) or chips at the silicon level. Their work includes activities such as architecture definition, circuit design, verification, and optimization for performance and power efficiency. SMTS engineers often lead technical projects, mentor junior engineers, and contribute to the overall innovation in semiconductor technology. They typically work for companies in the semiconductor, electronics, or related industries. This role requires deep expertise in hardware design, tools like Verilog or VHDL, and a strong understanding of fabrication processes.
More about Smts Silicon Design Engineer jobs

Silicon CAD Engineer, University Graduate, PhD

Google

Sunnyvale, CA • On-site

Full-time

Posted 17 days ago


Google rating

8.8

Company rating: 8.8 out of 10

Based on 92 frontline employees who took The Breakroom Quiz

31st of 186 rated software companies


Job description

Minimum qualifications:
  • PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • Experience in Verilog, SystemVerilog, or equivalent hardware description language.
  • Experience with scripting for automation (e.g., shell, Python, Perl).
  • Experience in one or more of the following: silicon design/verification, FPGA design/verification, or EDA tools.

Preferred qualifications:
  • 1 year experience coding in one of the following programming languages including but not limited to: C, C , Python, or Java.
  • Experience in one or more of the following: SoC architecture, embedded systems, firmware design.
  • Experience in applying AI techniques to software or hardware development.
  • Ability to start full-time role in 2026.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on chips powering the next generation of Google Cloud systems. You will work well both separately and as part of a team.
In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed Electronic Design Automation (EDA) tools, custom tooling, and emergent technologies from GDM and core.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target bonus equity benefits
Learn more about benefits at Google .
Responsibilities
  • Collaborate in or lead projects to identify automation opportunities, analyze potential approaches, develop custom tooling or flows implementing existing first-party/third-party tools, and support deployment of the resulting solutions across global sites.
  • Study, diagnose, and review technical issues by collaborating with silicon and software engineers and third-party EDA and IP vendors to analyze the sources of the issues and the impacts on user productivity.
  • Develop and review code developed by other team members and users to provide feedback, ensuring best practices are followed.
  • Write documents that set new technical directions. Contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
  • Leverage AI to both speed the development of tools and development flows, providing more natural and higher-efficiency ways for users to interact with developed technologies.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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