1

Senior Asic Design Engineer Jobs in Colorado (NOW HIRING)

Broadcom's ASIC Products Division is seeking a Design Automation Software Development Engineer in the Design For Test (DFT) team developing SoC ASIC products. They will define, develop, deploy and ...

Job #216852 Chipton-Ross is seeking an FPGA Design Engineer for a contract opportunity in Littleton ... ASIC/FPGA verification experience with modern verification methodologies such as UVM, OVM or VMM ...

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

As a Staff Electrical Engineer, you will work with cross-functional design and development teams to ... Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ...

Staff FPGA Design Engineer

Berthoud, CO · On-site

$123K - $169K/yr

As a Staff Electrical Engineer, you will work with cross-functional design and development teams to ... Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ...

Staff FPGA Design Engineer

Berthoud, CO

$123K - $169K/yr

As a Staff Electrical Engineer, you will work with cross-functional design and development teams to ... Architect and generate ASIC/FPGA RTL code * Generate test cases and run simulations to verify ...

Broadcom is seeking an experienced IC Package Design Manager to lead a team of engineers designing ... How the substrate and package fit into the overall ASIC design and manufacturing flows * Design ...

$123K - $169K/yr

As an ASIC & FPGA Associate Engineering Manager , you will lead and manage a team of ASIC/FPGA design and verification engineers in executing design services for programs in the integration and test ...

Showing results 21-40

Senior Asic Design Engineer information

See Colorado salary details

$147.2K

$186.8K

$230.8K

How much do senior asic design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for senior asic design engineer in Colorado is $186,806.00, according to ZipRecruiter salary data. Most workers in this role earn between $167,200.00 and $205,000.00 per year, depending on experience, location, and employer.

What does a senior ASIC design engineer do?

A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.

What are the key skills and qualifications needed to thrive as a senior ASIC design engineer?

To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.

What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?

AspectSenior Asic Design EngineerDigital IC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC designBachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design
Work EnvironmentDesign teams in semiconductor or tech companies, hardware development labsIntegrated circuit design teams, research labs, semiconductor companies
Employer & Industry UsageUsed in ASIC development, FPGA design, hardware accelerationUsed in digital chip design, FPGA development, digital system integration

The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.

What are some common challenges senior ASIC design engineers face when collaborating with cross-functional teams?

Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
What are the most commonly searched types of Asic Design Engineer jobs in Colorado? The most popular types of Asic Design Engineer jobs in Colorado are:
What are popular job titles related to Senior Asic Design Engineer jobs in Colorado? For Senior Asic Design Engineer jobs in Colorado, the most frequently searched job titles are:
What job categories do people searching Senior Asic Design Engineer jobs in Colorado look for? The top searched job categories for Senior Asic Design Engineer jobs in Colorado are:
What cities in Colorado are hiring for Senior Asic Design Engineer jobs? Cities in Colorado with the most Senior Asic Design Engineer job openings:
What are popular job titles related to Senior Asic Design Engineer jobs in CO? For Senior Asic Design Engineer jobs in CO, the most frequently searched job titles are:
Infographic showing various Senior Asic Design Engineer job openings in Colorado as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $186,806 per year, or $89.8 per hour.

ASIC Digital Physical Design Manager

Keysight Technologies, Inc.

Colorado Springs, CO • On-site

$134K - $138K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 9 days ago


Keysight Technologies rating

8.1

Company rating: 8.1 out of 10

Based on 20 frontline employees who took The Breakroom Quiz

49th of 156 rated electronics manufacturers


Job description

Overview
Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.
Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.
This role sits within Keysight Laboratories-a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You'll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs.
A sustained driver of Keysight's success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team-overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development.
The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life-immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.
Responsibilities
  • Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
  • Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
  • Oversee physical implementation for digital, mixed-signal, and third-party IP-from block to subsystem to top-level integration-including place and route, timing closure, and power closure.
  • Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
  • Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
  • Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
  • Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
  • Own project execution across the physical design lifecycle-planning, resourcing, schedules, milestones, and risk mitigation-to deliver predictable tapeouts and product readiness.

Qualifications
Must-have Qualifications
  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications
  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight's ability to obtain any required government authorizations.
We are unable to support visa sponsorship for this position.
MIN $151,000.00 - MAX $253,000.00
Most offers will be between the minimum and the midpoint of the Salary Range listed above.
#LI-MO1
Note: For other locations, pay ranges will vary by region
US Employees may be eligible for the following benefits:
  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

What Keysight Technologies employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom