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Semiconductor Process Integration Engineer Jobs in New York

GlobalFoundries

Quantum PDK Engineer

New York, NY · On-site

$98K - $176K/yr

Collaborate cross-functionally with device, process, integration, and EDA teams to align design ... Strong knowledge of semiconductor device physics and electronic devices * Experience with EDA tools ...

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Semiconductor Process Integration Engineer information

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$54.2K

$100.7K

$155.9K

How much do semiconductor process integration engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for semiconductor process integration engineer in New York is $100,670.00, according to ZipRecruiter salary data. Most workers in this role earn between $81,500.00 and $112,700.00 per year, depending on experience, location, and employer.

What are the typical daily responsibilities of a semiconductor process integration engineer?

As a Semiconductor Process Integration Engineer, your daily tasks usually involve coordinating with process and device engineers, analyzing production data, and troubleshooting yield or performance issues in semiconductor manufacturing. You may develop and optimize process flows, work on root cause analyses for defects, and implement new technologies to improve device performance. Routine meetings with cross-functional teams—such as design, process engineering, and quality assurance—are common, and your role often includes documenting experimental results and preparing technical presentations. This hands-on, dynamic work environment fosters both technical growth and opportunities to contribute directly to product quality and innovation.

What are the key skills and qualifications needed to thrive as a semiconductor process integration engineer?

To thrive as a Semiconductor Process Integration Engineer, you need a solid understanding of semiconductor device physics, fabrication processes, and materials science, often requiring at least a bachelor's or master's degree in electrical engineering, materials science, or a related field. Proficiency with semiconductor process simulation tools (such as TCAD), data analysis software, and familiarity with cleanroom protocols is essential. Effective communication, problem-solving, and strong project management skills set outstanding candidates apart. These competencies are crucial for optimizing process flows, troubleshooting production issues, and fostering successful collaboration in a multidisciplinary manufacturing environment.

What is a semiconductor process integration engineer?

A Semiconductor Process Integration Engineer is responsible for developing and optimizing semiconductor fabrication processes by integrating various process modules, such as lithography, etching, deposition, and CMP. They work closely with design, process, and equipment engineers to ensure device performance, yield, and manufacturability. Their role involves data analysis, troubleshooting process issues, and continuous improvement of semiconductor manufacturing. Additionally, they help with technology transfers and scaling processes for high-volume production.

What are popular job titles related to Semiconductor Process Integration Engineer jobs in New York? For Semiconductor Process Integration Engineer jobs in New York, the most frequently searched job titles are:
What job categories do people searching Semiconductor Process Integration Engineer jobs in New York look for? The top searched job categories for Semiconductor Process Integration Engineer jobs in New York are:
Semiconductor Process Integration Engineer jobs near you
Infographic showing various Semiconductor Process Integration Engineer job openings in New York as of June 2026, with employment types broken down into 99% Full Time, and 1% Contract. Highlights an 88% Physical, 3% Hybrid, and 9% Remote job distribution, with an average salary of $100,670 per year, or $48.4 per hour.

Quantum PDK Engineer

GlobalFoundries

New York, NY • On-site

$98K - $176K/yr

Full-time

Re-posted 3 days ago

GlobalFoundries rating

8.3

Company rating: 8.3 out of 10

Based on 35 frontline employees who took The Breakroom Quiz

67th of 536 rated manufacturers

Job description

Quantum PDK design enablement.
About GlobalFoundries
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Introduction
The Quantum PDK Design Enablement (MTS) role is a technical contributor within the Quantum Technology Solutions organization focused on enabling scalable quantum computing platforms. This position supports development of Process Design Kits (PDKs), compact models, and design enablement infrastructure that bridge advanced quantum device physics with semiconductor manufacturing and circuit design, including cryogenic control and readout ICs. This role operates at the intersection of device physics, modeling, and EDA, translating emerging quantum device technologies into usable, manufacturable, and customer-ready design environments.
Summary of Role
As a Member of Technical Staff, this role contributes to the development, deployment, and support of PDKs for quantum device platforms and associated cryogenic electronics. The engineer will work on compact modeling, device libraries, test chip development, and EDA integration, ensuring accurate, validated, and production-ready design collateral. The position emphasizes hands-on technical execution, automation, and strong cross-functional collaboration across device engineering, process integration, modeling, and design teams to enable scalable and high-performance quantum systems.
Essential Responsibilities
  • Develop, deploy, and maintain PDKs (tech files, model files, rule decks, runtime code) for quantum devices and cryogenic control/readout ICs
  • Create device libraries and parameterized cells (PCells), translating process design rules and SPICE/model specifications into design-ready implementations
  • Support compact model development, parameter extraction, and correlation across TCAD, silicon data, and cryogenic characterization
  • Integrate and validate PDKs within EDA environments (e.g., LVS/DRC, simulation flows), including development of automation tools representing fab processes
  • Design test structures and test chips, and develop validation plans to ensure model accuracy and silicon correlation
  • Develop and execute QA workflows, including DRC/LVS test cases and release validation, to ensure high-quality customer deliveries
  • Analyze device and circuit data to identify variability, reliability risks, and performance trends; support yield-learning and root-cause analysis
  • Create and maintain PDK documentation (release notes, application notes, known issues) and communicate usage guidance to users
  • Collaborate cross-functionally with device, process, integration, and EDA teams to align design enablement with technology capabilities
  • Contribute innovative ideas that may lead to intellectual property, patents, or advanced design enablement methodologies

Other Responsibilities:
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications
  • BS (MS preferred) in Electrical Engineering, Microelectronics, Physics, Computer Science, or related field
  • ~5-6+ years of experience in semiconductor design enablement, PDK development, or EDA
  • Strong knowledge of semiconductor device physics and electronic devices
  • Experience with EDA tools (e.g., Cadence Virtuoso or similar) and design flows
  • Experience with device modeling, test structures, or silicon validation
  • Familiarity with scripting (e.g., Python, Tcl, Perl) and Unix/Linux environments
  • Strong analytical, debugging, and problem-solving skills
  • Effective communication and teamwork skills; detail-oriented and self-motivated

Preferred Qualifications
  • Experience with Cadence SKILL, PCell development, and PDK architectures
  • Background in TCAD simulation and compact model correlation
  • Familiarity with variability modeling, SPC, or statistical analysis methods
  • Experience with cryogenic electronics or low-temperature device behavior
  • Exposure to quantum devices, superconducting systems, or quantum computing hardware
  • Experience working with EDA vendors or enabling custom design flows
  • Knowledge of ML/AI techniques applied to modeling or EDA workflows

Expected Salary Range
$98,000.00 - $176,000.00
The exact Salary will be determined based on qualifications, experience and location.
If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.
An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.
GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.
All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law

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