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Remote Chip Jobs (NOW HIRING)

MatX

SOC Architect (Remote)

Mountain View, CA · On-site +1

$175K - $450K/yr

We are seeking an experienced System-on-Chip (SoC) Architect to lead the design of our next ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Mercor

Circuit Design PhD - Problem Author

New York, NY · Remote

$85/hr

Remote Role Responsibilities * Author original, free-response engineering problems grounded in real ... Experience with well-known/blue-chip employers. Application Process (Takes 20-30 mins to complete)

MatX

Software Engineer - Simulators

Mountain View, CA · On-site +1

$175K - $362K/yr

Design and implement a Rust-based chip simulator, building a cycle-accurate model of our custom ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Mercor

Mechanical Design PhD - CAD Expert

New York, NY · Remote

$85/hr

Remote Role Responsibilities * Author original, free-response engineering problems grounded in real ... Experience with well-known/blue-chip employers. Application Process (Takes 20-30 mins to complete)

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Remote Chip information

What is a remote chip?

Remote chip jobs typically refer to positions in the semiconductor or microchip industry that can be performed remotely. These roles may include chip design, verification, software development for chips, or remote technical support and testing. Advancements in collaborative tools and secure remote access have enabled professionals in this field to work from locations outside traditional labs or offices. However, some hands-on tasks, such as physical fabrication and certain types of hardware testing, still require on-site presence. Remote chip jobs are increasingly popular as companies embrace flexible work arrangements.

What are the key skills and qualifications needed to thrive as a remote chip engineer, and why are they important?

To thrive as a Remote Chip Engineer, you need a strong background in electrical engineering, digital and analog circuit design, and semiconductor fundamentals, typically supported by a relevant degree. Proficiency with EDA tools (such as Cadence, Synopsys, or Mentor Graphics), HDL languages (Verilog/VHDL), and familiarity with remote collaboration platforms is essential. Excellent problem-solving skills, attention to detail, and effective communication are crucial for coordinating with distributed teams and troubleshooting complex issues. These skills ensure efficient chip development, seamless teamwork, and high-quality deliverables in a remote work environment.

What are some common challenges faced when working remotely as a chip designer, and how can they be overcome?

Remote Chip Designers often face challenges related to collaboration and access to specialized hardware or lab equipment. Communication can be more complex when discussing intricate design details with distributed teams, and resolving technical issues may require creative remote troubleshooting. To overcome these challenges, it's important to leverage collaborative design tools, maintain clear documentation, and schedule regular video meetings with team members. Many companies also offer remote access to simulation environments and provide virtual lab resources to support remote work.
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What states have the most Remote Chip jobs?

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Remote Chip jobs near you
Infographic showing various Remote Chip job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 9% Part Time, 1% Contract, and 1% Nights. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution.

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

Santa Clara, CA • Remote

$100K - $500K/yr

Full-time

Posted 2 days ago

New

Job description

Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

  • A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
  • Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
  • Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
  • Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
  • A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

  • Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
  • Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
  • Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
  • Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
  • Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
  • Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
  • Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You'll Learn

  • How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
  • Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
  • Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
  • How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

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