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Power Management Ic Design Jobs (NOW HIRING)

indie

Digital IC Design Engineer

Aliso Viejo, CA · On-site

$145K/yr

As a Digital IC Design Engineer you will be responsible for managing and executing activities ... power management. * Drive and/or support the implementation of innovative security features for ...

Coherent

Lead IC Design Engineer

Santa Clara, CA · Hybrid

$238K/yr

Plan & manage evaluation of prototype silicon in close collaboration with the application and ... power detectors, VGAs. * Good understanding of S-parameters, transmission lines, IC design ...

II-VI Incorporated

Lead IC Design Engineer

Santa Clara, CA · Hybrid

$238K/yr

Plan & manage evaluation of prototype silicon in close collaboration with the application and ... power detectors, VGAs. * Good understanding of S-parameters, transmission lines, IC design ...

onsemi

MTS Digital Design Engineer

San Jose, CA · On-site

$159K/yr

This group is responsible for development of Power management products including Multiphase ... Lead a Digital IC design team with product ownership and responsibility from definition to release ...

onsemi

MTS Digital Design Engineer

San Jose, CA · On-site

$159K/yr

This group is responsible for development of Power management products including Multiphase ... Lead a Digital IC design team with product ownership and responsibility from definition to release ...

AttoTude

Mixed-Signal CMOS IC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

Strong background in analog and digital mixed-signal design, including charge pumps, power control ... Strong communication, leadership, and project management skills Education: * Master's Degree (MEng ...

BitDeer

Analog IC Mixed-Signal Engineer

San Jose, CA · On-site

$150K - $250K/yr

Drive development of sophisticated mixed-signal circuits, including PLLs, power management units ... Design and Verification: Direct the characterization and maintenance of standard cell libraries ...

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Power Management Ic Design information

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$53.5K

$116K

$149.5K

How much do power management ic design jobs pay per year?

As of Jun 17, 2026, the average yearly pay for power management ic design in the United States is $116,016.00, according to ZipRecruiter salary data. Most workers in this role earn between $116,500.00 and $116,500.00 per year, depending on experience, location, and employer.

What is a Power Management IC Design job?

A Power Management IC (PMIC) Design job involves designing integrated circuits that regulate and distribute power efficiently in electronic devices. Engineers in this role develop circuits for voltage regulation, power conversion, and battery management while optimizing performance and minimizing power loss. They work with semiconductor technologies, simulation tools, and testing methodologies to ensure reliability and efficiency. PMIC designers collaborate with system architects and layout engineers to meet the power requirements of applications like smartphones, IoT devices, and automotive systems.

What are the key skills and qualifications needed to thrive in the Power Management Ic Design position, and why are they important?

Success in Power Management IC Design requires a strong background in analog and mixed-signal circuit design, semiconductor device physics, and a relevant degree in electrical or electronics engineering. Familiarity with EDA tools like Cadence or Synopsys, experience in silicon validation, and sometimes certifications in low-power design techniques are highly valued. Excellent problem-solving skills, attention to detail, and effective teamwork are important soft skills that distinguish top designers. Mastery of these abilities ensures high-performance, reliable power solutions in increasingly complex electronic systems.

What does a typical day look like for a Power Management IC Design engineer?

A typical day for a Power Management IC Design engineer involves designing, simulating, and verifying integrated circuits dedicated to efficient power conversion and regulation. You’ll frequently collaborate with cross-functional teams such as layout, digital design, and test engineering, ensuring your designs are robust and manufacturable. Tasks may include schematic capture, design reviews, debugging silicon prototypes, and interacting with customers or product managers to meet project requirements. The role offers a dynamic blend of hands-on technical work and collaborative problem-solving, making each day both challenging and rewarding for those passionate about electronics innovation.

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What cities are hiring for Power Management Ic Design jobs? Cities with the most Power Management Ic Design job openings:
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Power Management Ic Design jobs near you
Infographic showing various Power Management Ic Design job openings in the United States as of June 2026, with employment types broken down into 2% Internship, 93% Full Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $116,016 per year, or $55.8 per hour.
Principal Design Engineer

Principal Design Engineer

Navitas Semiconductor

Torrance, CA

Full-time

Medical, Dental, Vision, PTO

Posted 8 days ago

Job description

Job Purpose:
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC design engineer to lead the architecture, design, and silicon execution of next-generation power management ICs. This role is hands-on and technical, with end-to-end ownership from concept through production, and close collaboration with systems, device, layout, and validation teams. This is a key technical expert position for engineers who have successfully brought power ICs into high-volume production and want to shape future architectures.


Key Responsibilities and Duties:
• Lead the architecture, design, and verification of power management ICs from transistor-level blocks to full top-level integration.
• Define and evaluate system-level trade-offs for next-generation power supplies in collaboration with applications and systems teams.
• Drive IC architecture decisions for products including AC-DC, DC-DC, ACF, LLC, QR, and related power topologies.
• Interface closely with device, modeling, and EDA teams to optimize device selection, models, and simulation methodologies.
• Guide and review physical layout and floor planning, providing clear feedback to ensure optimal performance, reliability, and manufacturability.
• Own tape-out execution, ensuring designs meet performance, schedule, and quality requirements.
• Lead silicon bring-up, lab validation, debugging, and correlation versus simulation.
• Support yield improvement, failure analysis, and release to production.
• Mentor junior designers and contribute to best practices across the design organization.

Knowledge, Skills, Abilities, and Other Characteristics (KSAO’s)
• Proven experience as chip lead or technical owner on at least one successful silicon program.
• Demonstrated track record of delivering power ICs from concept to high-volume production, including:
     o Architecture definition
     o Circuit design
     o Layout supervision
     o Post-extraction verification
     o Lab characterization and debug
     o Yield and failure analysis support
• Strong experience in AC-DC and/or DC-DC power IC design.
• Deep expertise in analog and mixed-signal building blocks such as:
     o Bandgap references
     o LDOs
     o Comparators
     o Charge pumps
     o Operational amplifiers
• Clear written and verbal communication skills.
• Self-motivated, collaborative, and comfortable working in a fast-paced, startup-like environment.


Required Qualifications
Basic 
• Degree in Electrical Engineering, Material Science, Applied Physics or related Fields
• Strong understanding of semiconductor device physics, SOA, and power transistors used in high-frequency switching.
• Solid knowledge of silicon fabrication processes and their impact on device models and circuit performance.


Preferred: 
• MSEE + 7+ years or PhD + 5+ years of industry experience in analog or mixed-signal IC design.
• Proficiency with EDA tools, including:
     o Cadence Virtuoso / Spectre
     o Post-parasitic extraction simulation
     o Monte Carlo and corner analysis
• Experience with DFT methodologies, characterization strategies, and production test planning.
• Hands-on lab experience with silicon validation, debug, and characterization.


What We Give:
• A high visibility opportunity to work on leading edge technology development with a mission to make the world better with advancing the technology that powers the future.
• Fast decision making and freedom to work on interesting problems that the world cares about.
• A mission to succeed with full support from management.
• Health, dental, and vision benefits, unlimited PTO 
• Total Compensation includes base + bonus and stock awards, depending on experience

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