Job Title: Principal Software Engineer, Linux PCIe Device Drivers Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2370 ...
Job Title: Principal Software Engineer, Linux PCIe Device Drivers Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2370 ...
Join our PCIe software team as a Staff Embedded Software Customer Engineer and play a pivotal role in advancing high-performance interconnect technologies. In this role, you will: * Collaborate on ...
Join our PCIe software team as a Staff Embedded Software Customer Engineer and play a pivotal role in advancing high-performance interconnect technologies. In this role, you will: * Collaborate on ...
Principal Software Engineer, Linux PCIe Device Drivers (AI2370)
San Jose, CA · On-site
$220K - $296K/yr
Principal Software Engineer, Linux PCIe Device Drivers Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2370 Description The SoC ...
Principal Software Engineer, Linux PCIe Device Drivers (AI2370)
San Jose, CA · On-site
$220K - $296K/yr
Principal Software Engineer, Linux PCIe Device Drivers Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office) Job ID: AI2370 Description The SoC ...
HW INTERFACE ( SOMEONE WHO HAS EXPERIENCE WITH ANY ON THE PROTOCOLS, LIKE USB, PCIE, SATA) ENVIRONMENT : LINUX WE NEED A CANDIDATE WHO IS MASTER IN C++, WITH EXPERIENCE IN HW INTERFACE EXPERIENCE AND ...
HW INTERFACE ( SOMEONE WHO HAS EXPERIENCE WITH ANY ON THE PROTOCOLS, LIKE USB, PCIE, SATA) ENVIRONMENT : LINUX WE NEED A CANDIDATE WHO IS MASTER IN C++, WITH EXPERIENCE IN HW INTERFACE EXPERIENCE AND ...
Senior Firmware Engineer - PCIe/CXL Memory Solutions
San Jose, CA · On-site
$140K - $185K/yr
Astera Labs' Intelligent Connectivity Platform integrates CXL ® , Ethernet, NVLink, PCIe ® , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse ...
Senior Firmware Engineer - PCIe/CXL Memory Solutions
San Jose, CA · On-site
$140K - $185K/yr
Astera Labs' Intelligent Connectivity Platform integrates CXL ® , Ethernet, NVLink, PCIe ® , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse ...
Technology Manager/Product Planner - PCIe and DDR
$150K - $210K/yr
The Technology Manager for PCIe and DDR will work on the forefront of technology with leading industry players, Rohde & Schwarz (R&S) global sales teams, and R&S global development teams. The ...
Technology Manager/Product Planner - PCIe and DDR
$150K - $210K/yr
The Technology Manager for PCIe and DDR will work on the forefront of technology with leading industry players, Rohde & Schwarz (R&S) global sales teams, and R&S global development teams. The ...
Firmware Architect - High-Speed Interconnect (PCIe / OCI)
Austin, TX · On-site
$185K/yr
This role will focus on PCIe Gen 6/7/8 and emerging Optical Component Interconnect (OCI) technologies, driving scalable, high-performance, and robust solutions across AMD's server platforms. You will ...
Firmware Architect - High-Speed Interconnect (PCIe / OCI)
Austin, TX · On-site
$185K/yr
This role will focus on PCIe Gen 6/7/8 and emerging Optical Component Interconnect (OCI) technologies, driving scalable, high-performance, and robust solutions across AMD's server platforms. You will ...
This role will focus on PCIe Gen 6/7/8 and emerging Optical Component Interconnect (OCI) technologies, driving scalable, high-performance, and robust solutions across AMD's server platforms. You will ...
This role will focus on PCIe Gen 6/7/8 and emerging Optical Component Interconnect (OCI) technologies, driving scalable, high-performance, and robust solutions across AMD's server platforms. You will ...
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good understanding of silicon design and computer architecture, knowledge of physical design, experience in ...
A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good understanding of silicon design and computer architecture, knowledge of physical design, experience in ...
Senior GPU PCIe and Boot Architect
Santa Clara, CA · On-site
$152K - $206K/yr
We are looking for a Senior GPU PCIe and Boot architect. NVIDIA is seeking outstanding engineers to design the architecture and infrastructure for boot, PCIe/CXL enumeration, and capability discovery.
Senior GPU PCIe and Boot Architect
Santa Clara, CA · On-site
$152K - $206K/yr
We are looking for a Senior GPU PCIe and Boot architect. NVIDIA is seeking outstanding engineers to design the architecture and infrastructure for boot, PCIe/CXL enumeration, and capability discovery.
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the ...
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the ...
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the ...
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Senior Design engineer to join our PCIe, CXL IP design team. Candidates will be joining some of the ...
As a System Development Engineer on the PCIe and Signal Integrity team within the Core Components Organization, you will work on next-generation high-speed designs for server components and systems.
As a System Development Engineer on the PCIe and Signal Integrity team within the Core Components Organization, you will work on next-generation high-speed designs for server components and systems.
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Own and drive PCIE/CXL subsystem micro-architecture definition, RTL implementation, and integration * Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Senior Staff Design Verification Engineer - PCIE/CXL Sub-System
Irvine, CA · On-site
$146K - $178K/yr
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Senior Staff Design Verification Engineer - PCIE/CXL Sub-System
Irvine, CA · On-site
$146K - $178K/yr
Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems , from test planning through coverage closure and signoff * Define and execute comprehensive verification plans based on ...
Pcie information
See salary details
$11.06 - $12.04
4% of jobs
$12.04 - $13.02
19% of jobs
$13.27 is the 25th percentile. Wages below this are outliers.
$13.02 - $14.01
7% of jobs
$14.01 - $14.99
11% of jobs
The median wage is $15.43 / hr.
$14.99 - $15.97
20% of jobs
$15.97 - $16.96
14% of jobs
$17 is the 75th percentile. Wages above this are outliers.
$16.96 - $17.94
6% of jobs
$17.94 - $18.92
5% of jobs
$18.92 - $19.91
9% of jobs
$19.91 - $20.89
3% of jobs
$20.89 - $21.88
1% of jobs
$11
$15
$21
How much do pcie jobs pay per hour?
What is the difference between Pcie vs Network Technician?
| Aspect | Pcie | |
|---|---|---|
| Required Credentials | Typically requires a computer hardware or IT certification, such as CompTIA A+ or Network+ | Requires networking certifications like CompTIA Network+ or Cisco CCNA |
| Work Environment | Works primarily inside data centers, server rooms, or hardware labs | Works in offices, data centers, or client sites troubleshooting network issues |
| Industry Usage | Commonly used in hardware manufacturing, data centers, and IT infrastructure | Used across various industries for maintaining and troubleshooting networks |
While Pcie focuses on hardware interfaces within computers, Network Technicians specialize in network systems and connectivity. Both roles require technical certifications and work in IT environments, but Pcie is hardware-centric, whereas Network Technicians handle network setup and troubleshooting.

$220K - $296K/yr
Full-time
Posted 7 days ago
Job description
- Leverage IP SW and integrate into MLSoCâ„¢ SW environment.
- Develop drivers for End Point, Root Complex and PCIe Bifurcation modes for the embedded system.
- Test and verify Linux PCIe device drivers and environment with Virtualizers and Zebu emulators.
- Design, Implement and Test Host drivers, libraries and test applications to interface to SiMa.ai’s MLSoC™
- Experience integrating GPUs, NVME drives, and other PCIe devices to a Host Root Complex system.
- Configure Linux environments for different reference boards.
- Modify and perform Yocto builds for new functionality.
- Provide SW to support HW MLSoC test validation team.
- Own the overall design of the data transfer and data structures used for management and data transfer over PCIe.
- BS/MS in computer science with minimum of 10+ years of experience
- Hands-on, production deployed experience developing firmware, boot code and SW using high performance 64 bit Arm processors.
- Hands-on, production deployed experience developing drivers for PCIe End Point and Root Complex embedded systems.
- Development experience (preferably production deployed) with x86 Linux Host systems to communicate with PCIe EP devices.
- Hands-on experience bringing up and troubleshooting new PCIe devices.
- Development experience with Embedded Linux (e.g., Yocto) and embedded RTOS (e.g., QNX) is highly desirable
- Experience in working with silicon teams is highly desirable.
- Good proficiency with C/C++
- Proven track record and experience building and delivering complex SW products.