ZipRecruiter

Log In

1

Package Design Engineer Jobs in California (NOW HIRING)

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

Required Qualifications * BS or MS in Electrical Engineering, or equivalent practical background. * 6+ years of IC package physical design, including at least one product taken from concept through ...

Edge Autonomy

Packaging Design Engineer

San Luis Obispo, CA · On-site

$106K - $142K/yr

Convert engineering requirements and CAD models into complete packaging designs, drawings and specifications. * Conduct and document validation testing (drop, vibration, shock, environmental, transit ...

NVIDIA Gruppe

Senior SOC Design Engineer

Santa Clara, CA · On-site

$136 - $218.50/hr

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs and partnering with experts in ASIC design, Physical Design, CAD, Package Design, Software, DFT ...

Broadcom Inc.

ASIC Package Design Manager

San Jose, CA · On-site

$143.80 - $230/hr

Broadcom is seeking an experienced IC Package Design Manager to lead a team of engineers designing complex flip‑chip‑BGA packages for industry‑leading ASICs with high‑speed SerDes and very ...

Broadcom

ASIC Package Design Manager

San Jose, CA

Broadcom is seeking an experienced IC Package Design Manager to lead a team of engineers designing complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power ...

Broadcom, Inc.

ASIC Package Design Manager

San Jose, CA · On-site

Broadcom is seeking an experienced IC Package Design Manager to lead a team of engineers designing complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power ...

previous page

Showing results 41-60

All JobsPackage Design Engineer JobsPackage Design Engineer Jobs in California

Package Design Engineer information

See California salary details

$88.8K

$134.7K

How much do package design engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for package design engineer in California is $133,271.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $134,200.00 per year, depending on experience, location, and employer.

Are packaging design engineers in demand?

Packaging design engineers are in demand due to the growth of consumer goods, e-commerce, and sustainable packaging initiatives. They often require skills in CAD software and knowledge of materials, with employment opportunities available in manufacturing, branding, and product development sectors.

How does a package design engineer collaborate with cross-functional teams during product development?

Package Design Engineers regularly work with product development, manufacturing, and marketing teams to ensure that packaging solutions meet technical specifications, production capabilities, and branding requirements. This collaboration often involves attending design review meetings, sharing prototypes, and integrating feedback from multiple stakeholders. Effective communication and adaptability are crucial, as engineers must balance functional, cost, and aesthetic considerations throughout the development process.

What is the difference between Package Design Engineer vs Packaging Designer?

AspectPackage Design EngineerPackaging Designer
CredentialsBachelor's in Packaging Engineering, Mechanical Engineering, or related fieldsBachelor's in Graphic Design, Industrial Design, or Packaging Design
Work EnvironmentManufacturing facilities, R&D labs, engineering teamsDesign studios, marketing departments, creative agencies
Industry UsageConsumer goods, electronics, pharmaceuticals, food productsConsumer products, branding, marketing campaigns

The Package Design Engineer focuses on developing functional, cost-effective, and manufacturable packaging solutions, often working closely with engineering teams. Packaging Designers primarily concentrate on the visual appeal, branding, and creative aspects of packaging. Both roles may collaborate, but their core responsibilities and skill sets differ significantly.

What skills and qualifications are needed to be a package design engineer?

To thrive as a Package Design Engineer, a strong background in engineering, materials science, and design principles—often supported by a bachelor's degree in mechanical, packaging, or industrial engineering—is essential. Familiarity with CAD software, prototyping tools, and simulation systems, as well as knowledge of industry standards like ISTA or ASTM, is typically required. Creativity, problem-solving, and effective communication distinguish top performers in this field. These skills are crucial for developing innovative, cost-effective, and functional packaging solutions that meet product, manufacturing, and regulatory requirements.

What does a package design engineer do?

A Package Design Engineer is responsible for designing and developing packaging solutions for products, ensuring that they are both functional and visually appealing. This role involves selecting appropriate materials, considering factors like cost, durability, and environmental impact, as well as collaborating with product development, marketing, and manufacturing teams. Package Design Engineers also conduct tests to ensure packaging protects the product during shipping and storage, and they often use computer-aided design (CAD) software to create prototypes. Their work is crucial for both product safety and brand image.

What are popular job titles related to Package Design Engineer jobs in California?

For Package Design Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Package Design Engineer jobs in California look for?

The top searched job categories for Package Design Engineer jobs in California are:

Package Design Engineer jobs near you
Infographic showing various Package Design Engineer job openings in California as of August 2026, with employment types broken down into 1% As Needed, 74% Full Time, 13% Part Time, 2% Temporary, and 10% Contract. Highlights an 93% Physical, 3% Hybrid, and 4% Remote job distribution, with an average salary of $133,271 per year, or $64.1 per hour.

Package Design & Layout Engineer

Cspeed

Palo Alto, CA • On-site

Full-time

Posted 11 days ago

Job description

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true "scale-up" architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
The Role
You will own the physical design of our optical engine packages - redistribution layers, substrate, and the bump and ball maps that tie the die stack to the host board. This is a hands-on layout role with real architectural influence.
You will work between our PIC and EIC design teams, our SI/PI and thermal engineers, and our supply chain (wafer fab, substrate vendor, OSAT). You will not be handed a finished floorplan to route - you will help define it.
What You'll Do
Layout execution
  • Deliver RDL/UBM and package substrate layouts for our optical engine products and test vehicles, from floorplan through tape-out.
  • Define and release bump maps, ball maps, and escape routing strategies for multi-die assemblies (PIC, EIC, and light source die).
  • Design to 200G/lane-class electrical requirements: differential pair routing, reference-plane integrity, crosstalk isolation, and power delivery for high-current, low-noise rails.

Co-design and floor planning
  • Participate from concept phase: produce preliminary floorplans and stack-up proposals that reconcile electrical, optical, thermal, and mechanical constraints before they are frozen.
  • Iterate with SI/PI engineers on test routes to converge routing topologies and design rules.

Design rules, DFM, and supplier engagement
  • Work directly with wafer fabs, substrate suppliers, and OSATs to capture and negotiate design rules, stack-ups, and assembly constraints.
  • Generate fab and assembly release packages; drive DFM/DFA closure and design reviews through to sign-off.
  • Flag rule conflicts early and propose alternatives rather than routing around them silently.

Verification and automation
  • Run and own physical verification: DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board.
  • Manage netlists for heterogeneous assemblies across revisions and product variants.
  • Build scripted automation (SKILL, Python, or equivalent) for repetitive layout, checking, and release tasks.

Build support
  • Support test vehicle definition, first builds, bring-up, failure analysis, and yield learning - including layout changes driven by assembly reality.
Required Qualifications
  • BS or MS in Electrical Engineering, or equivalent practical background.
  • 6+ years of IC package physical design, including at least one product taken from concept through tape-out and volume-relevant build.
  • Expert-level proficiency in a package layout tool: Cadence Allegro Package Designer / APD+ / SiP, Siemens Xpedition Package Designer, Synopsys IC Package, or equivalent.
  • Demonstrated experience with multi die packaging: 2D or 2.5/3D integration.
  • Working fluency with multi-layer organic substrate construction and how material and stack-up choices constrain routing.
  • Practical experience closing DFM/DFA with external substrate suppliers and OSATs.
  • Comfortable working in English across a distributed team and multiple time zones.
Preferred Qualifications
  • Demonstrated experience with advanced packaging: 2.5D/3D integration, RDL, TSV interposers, fan-out, microbump or Cu-pillar flip-chip.
  • Layout for 112G/224G SerDes or comparable high-speed interfaces; familiarity with signal and power integrity workflows (e.g. Cadence Sigrity/PowerSI, Ansys).
  • Familiarity with mask and RDL vendor flows, GDS-based layout environments (Virtuoso, KLayout), and AutoCAD file exchange.
  • Experience with package/IC co-design environments (e.g. Cadence Integrity 3D-IC).
  • Scripting for design automation and rule checking.
  • Experience at a startup or on a first-of-its-kind product, where the design rules did not exist yet.
Why This Role Is Different
Most package layout roles are a step in someone else's flow. Here, the package is the product. You will be one of a handful of people who determine whether a next-generation optical engine is manufacturable, and you will see your layout decisions land in silicon and in an OSAT line within months, not years.

Apply