Design Engineer V
Logan, UT · On-site +1
... verification using Meta's Design Traveler document. Create and modify engineering tool project ... templates, meta-data, configuration data, and rules. Technical Expertise & Problem Solving: Apply a ...
Design Engineer V
Logan, UT · On-site +1
... verification using Meta's Design Traveler document. Create and modify engineering tool project ... templates, meta-data, configuration data, and rules. Technical Expertise & Problem Solving: Apply a ...
New Grad RN Peds Infant Med Surg 3NE
Salt Lake City, UT · On-site
$32.27/hr
Those hired as a New Grad RN will work under a licensed RN until license can be verified. In conjunction with working on this unit New Grad RNs attend Intermountain's one-year nurse residency program.
New Grad RN Peds Infant Med Surg 3NE
Salt Lake City, UT · On-site
$32.27/hr
Those hired as a New Grad RN will work under a licensed RN until license can be verified. In conjunction with working on this unit New Grad RNs attend Intermountain's one-year nurse residency program.
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
Verification Test Engineer
UT · On-site
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
Verification Test Engineer
UT · On-site
Design, build, and commission test fixtures, rigs, and automated test equipment * Program and ... Write, review, and execute Engineering Verification Test (EVT), Design Verification Test (DVT), and ...
New Grad RN Peds Infant Med Surg 3NE
Salt Lake City, UT · On-site
$35.22/hr
Those hired as a New Grad RN will work under a licensed RN until license can be verified. In conjunction with working on this unit New Grad RNs attend Intermountain's one-year nurse residency program.
New
New Grad RN Peds Infant Med Surg 3NE
Salt Lake City, UT · On-site
$35.22/hr
Those hired as a New Grad RN will work under a licensed RN until license can be verified. In conjunction with working on this unit New Grad RNs attend Intermountain's one-year nurse residency program.
New
Senior FPGA Design Engineer
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... Experience with integration and debug of FPGA/ASIC devices * Radar processing techniques * Image ...
Senior FPGA Design Engineer
$116K - $160K/yr
Designs are verified against requirements using both directed test and constrained random ... Experience with integration and debug of FPGA/ASIC devices * Radar processing techniques * Image ...
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$140 - $190/hr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
New
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$140 - $190/hr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
New
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$154K - $161K/yr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$154K - $161K/yr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$154K - $161K/yr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
New
Lead, Software Engineer - FPGA
Salt Lake City, UT · On-site
$154K - $161K/yr
FPGA verification using simulation and unit testing * Experience developing in VHDL (preferred) or ... ASIC design experience is also applicable * Experience implementing industry-standard interfaces ...
New
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
We look for people who have bold new ideas, courage and a pioneering spirit to join forces to ... Experience with VHDL/FPGA/ASIC design * Experience with Nuclear Certified Design * Experience with ...
We look for people who have bold new ideas, courage and a pioneering spirit to join forces to ... Experience with VHDL/FPGA/ASIC design * Experience with Nuclear Certified Design * Experience with ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
We look for people who have bold new ideas, courage and a pioneering spirit to join forces to ... Experience with VHDL/FPGA/ASIC design * Experience with Nuclear Certified Design * Experience with ...
We look for people who have bold new ideas, courage and a pioneering spirit to join forces to ... Experience with VHDL/FPGA/ASIC design * Experience with Nuclear Certified Design * Experience with ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
Work closely with Design teams on verification, Test engineers on diagnostic accuracy, and Physical ... Experience in DFT and ATPG for SoC or ASIC designs * Experience utilizing industry-standard DFT ...
$35.22/hr
Nursing Grad - $32.27, New Grad RN - $35.22 * Shifts Available: Night and 50/50 *Must have less ... Education will be verified. * Basic Life Support (BLS) Certification for Healthcare Providers ...
New
$35.22/hr
Nursing Grad - $32.27, New Grad RN - $35.22 * Shifts Available: Night and 50/50 *Must have less ... Education will be verified. * Basic Life Support (BLS) Certification for Healthcare Providers ...
New
Oversee DVT (Design Verification Test) report generation and technical documentation * Coordinate with cross-functional teams including design engineering, manufacturing, and quality assurance
Oversee DVT (Design Verification Test) report generation and technical documentation * Coordinate with cross-functional teams including design engineering, manufacturing, and quality assurance
New Grad RN Med Surg
Sandy, UT · On-site
$35.22/hr
Nursing Grad - $32.27, New Grad RN - $35.22 Shift: NIGHTS Essential Functions * Demonstrates ... Education will be verified. * Basic Life Support (BLS) Certification for Healthcare Providers ...
New
New Grad RN Med Surg
Sandy, UT · On-site
$35.22/hr
Nursing Grad - $32.27, New Grad RN - $35.22 Shift: NIGHTS Essential Functions * Demonstrates ... Education will be verified. * Basic Life Support (BLS) Certification for Healthcare Providers ...
New
New Grad Asic Design Verification Engineer information
What does a new grad ASIC design verification engineer do?
A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.
What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?
To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.
What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?
| Aspect | New Grad Asic Design Verification Engineer | New Grad Digital Design Engineer |
|---|---|---|
| Required Skills | Hardware verification, simulation, scripting, HDL knowledge | Digital circuit design, HDL coding, logic design |
| Work Environment | Verification labs, simulation tools, hardware testing | Design teams, FPGA/ASIC development, coding |
| Industry Usage | Primarily in semiconductor and chip companies | Broadly in electronics, semiconductor, and tech firms |
While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.
What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?
New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
What are popular job titles related to New Grad Asic Design Verification Engineer jobs in Utah?
For New Grad Asic Design Verification Engineer jobs in Utah, the most frequently searched job titles are:
- Remote Asic Soc Design Engineer
- Internship Fpga Verification Engineer
- Remote Design Verification Engineer
- Junior Asic Verification Engineer
- Fpga Design Engineer
- Freelance Asic Verification Engineer
- Asic Design Engineer
- Remote Asic Design
- Work From Home Analog Mixed Signal Design Engineer
- Asic Fpga Design Engineer
What job categories do people searching New Grad Asic Design Verification Engineer jobs in Utah look for?
The top searched job categories for New Grad Asic Design Verification Engineer jobs in Utah are:
What cities in Utah are hiring for New Grad Asic Design Verification Engineer jobs?
Cities in Utah with the most New Grad Asic Design Verification Engineer job openings:
Job description
Request ID: 71044-1
Start/End Dates: 7/20/2026 - 12/25/2026
Tax Work Location: US - UT - Remote (144200)
Job Title: Core Engineering - Design Engineer V
Job Description: PCB Layout Engineer, AR Product Team
As a PCB Layout Engineer on Meta’s AR Product Team, you will be responsible for driving world-class, complex PCB layouts that incorporate cutting-edge component and stack-up technologies. A core focus of this role is implementing miniaturization solutions within AR product designs. You will collaborate closely with internal electrical and mechanical engineers, DFM, SiPi, and other layout and library teams, as well as external suppliers.
RESPONSIBILITIES
Project Management & Execution:
Manage multiple complex layout projects, providing timely status reports within Meta systems.
Lead designs from kick-off through tape-out, encompassing rigid, rigid-flex, and flex PCBs for both product and non-product/test projects.
Proactively schedule and drive project meetings (Kick-off, Placement, Constraint, and Design Reviews) to ensure design verification using Meta's Design Traveler document.
Create and modify engineering tool project templates, meta-data, configuration data, and rules.
Technical Expertise & Problem Solving:
Apply a solid understanding of electrical engineering principles, particularly for power distribution, high-speed circuits, and RF signals.
Identify project execution risks or slowdowns proactively and collaborate with managers and/or technical program managers to propose alternative PCB development workflow solutions.
Understand and propose practical fit and function solutions related to miniaturization concepts.
Cross-Functional Collaboration & Supplier Engagement:
Proactively partner with EE Leads, Mechanical Engineering, TPMs, and other cross-functional teams (XFNs) to resolve design issues.
Work with internal DFM engineers to confirm supplier requirements at project launch.
Engage with external suppliers and Supplier Quality/Process Engineering (SQE/PE) to resolve DFM issues and ensure high-yield builds.
MINIMUM QUALIFICATIONS
8+ years of experience in complex PCB Design.
5+ years of experience using Allegro PCB Design Tools (version 23.1 or newer).
Strong understanding of the mechanical aspects of electronics design.
Excellent communication skills.
Proficiency with Microsoft Office tools.
PREFERRED QUALIFICATIONS
BS in Electrical Engineering.
3+ years of experience implementing miniaturization solutions in dense form-factor designs (e.g., wearable products, mobile phone design).
About Infotech Sourcing
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
San Francisco, CA, US
Year founded
2004