As a Senior Circuit Design Engineer, you will leverage TSMC's leading process technology and design ... Design custom memory circuits and architectures tailored specifically for AI and HPC applications.
As a Senior Circuit Design Engineer, you will leverage TSMC's leading process technology and design ... Design custom memory circuits and architectures tailored specifically for AI and HPC applications.
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Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to ... Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help ...
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Advanced Package Design Engineer Office Location: San Jose, CA Work Model: Onsite About SK hynix ... Our cutting-edge memory technologies are essential in today's most advanced electronic devices and ...
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Advanced Package Design Engineer Office Location: San Jose, CA Work Model: Onsite About SK hynix ... Our cutting-edge memory technologies are essential in today's most advanced electronic devices and ...
Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to ... Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help ...
Quick apply
Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to ... Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help ...
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Advanced Package Design Engineer Office Location: San Jose, CA Work Model: Onsite About SK hynix ... Our cutting-edge memory technologies are essential in today's most advanced electronic devices and ...
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Product Design Engineer
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... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
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San Jose, CA · On-site
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
MICROARCHITECT AND RTL DESIGN ENGINEER SANTA CLARA, CA About the role: We are seeking a seasoned ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
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Senior VLSI CAD Engineer
Santa Clara, CA · Hybrid
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Senior VLSI CAD Engineer
Santa Clara, CA · Hybrid
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip ...
Product Design Engineer
San Jose, CA · On-site
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
Product Design Engineer
San Jose, CA · On-site
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
Senior VLSI CAD Engineer
Santa Clara, CA · On-site
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Senior VLSI CAD Engineer
Santa Clara, CA · On-site
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
Saratoga, CA · On-site
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
Saratoga, CA · On-site
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Quick apply
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. Description ... Preferred Qualifications Drive new memory system architectures from DRAM up. Explore architecture ...
FPGA Design Engineer
$129K - $178K/yr
Ability to collaborate with software engineers on hardware/software interfaces, including memory-mapped register design and interrupt architecture * Strong debugging skills using Vivado ILA, VIO, and ...
FPGA Design Engineer
$129K - $178K/yr
Ability to collaborate with software engineers on hardware/software interfaces, including memory-mapped register design and interrupt architecture * Strong debugging skills using Vivado ILA, VIO, and ...
FPGA Design Engineer
$135K - $225K/yr
Ability to collaborate with software engineers on hardware/software interfaces, including memory-mapped register design and interrupt architecture * Strong debugging skills using Vivado ILA, VIO, and ...
Quick apply
FPGA Design Engineer
$135K - $225K/yr
Ability to collaborate with software engineers on hardware/software interfaces, including memory-mapped register design and interrupt architecture * Strong debugging skills using Vivado ILA, VIO, and ...
Memory Design Engineer information
See California salary details
$94.7K is the 25th percentile. Wages below this are outliers.
$79.4K - $98.3K
31% of jobs
$98.3K - $117.1K
5% of jobs
The median wage is $130.7K / yr.
$117.1K - $136K
19% of jobs
$150.5K is the 75th percentile. Wages above this are outliers.
$136K - $154.8K
26% of jobs
$154.8K - $173.7K
13% of jobs
$173.7K - $192.5K
4% of jobs
$192.5K - $211.3K
0% of jobs
$211.3K - $230.2K
0% of jobs
$230.2K - $249K
0% of jobs
$249K - $267.9K
1% of jobs
$267.9K - $286.7K
1% of jobs
$79.4K
$139.5K
$286.7K
How much do memory design engineer jobs pay per year?
What are the primary challenges faced by Memory Design Engineers on a daily basis?
Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.
What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?
A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.
What engineers make $500,000?
What engineers make $200,000 a year?
What is the role of a memory design engineer?
What is a Memory Design Engineer job?
A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.
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Full-time
Posted 15 days ago
TSMC rating
8.0
Based on 21 frontline employees who took The Breakroom Quiz
46th of 142 rated electronics manufacturers
Job description
Step into a pivotal role within our San Jose design R&D team and position yourself at the forefront of the global semiconductor industry. As a Senior Circuit Design Engineer, you will leverage TSMC's leading process technology and design enablement solutions to push the boundaries of semiconductor manufacturing. In this role, you will focus on AI and high-performance computing applications, unleashing innovation and driving next-generation advancements. You will join us in our San Jose office, operating on a hybrid work schedule with 4 days in-office.
Responsibilities
- Design custom memory circuits and architectures tailored specifically for AI and HPC applications.
- Lead efforts in Power, Performance, and Area (PPA) optimization for custom SRAM circuits to align with advanced scaling advancements.
- Perform comprehensive technical analysis, including Time/Power/Area improvements, Read/Write margin, Noise, and Power/Signal IR/EM analysis.
- Provide supervised layout guidance, manage design characterization, and oversee methodology, verification, and final sign-off.
- Collaborate closely with RTL and Physical Design (PD) teams to ensure the best IP PPA integration.
- Handle compiler coding and the interpretation of testing results.
Minimum Qualifications
- Master's degree with 3+ years of relevant industry experience, or a Ph.D. demonstrating applicable academic research in VLSI design or custom circuits.
- In-depth knowledge of VLSI design, digital integrated circuits, Verilog, logic design, and DFT.
- Hands-on experience running SPICE simulations for custom circuits.
- A collaborative mindset with a strong teamwork attitude and excellent communication skills.
Preferred Qualifications
- Advanced knowledge of leading-edge process nodes (TSMC N7 and below), ideally with a track record of successfully delivering product tapeouts below 5nm.
- Deep expertise in high-speed and low-power custom SRAM or Register File architecture and implementation.
- Prior experience acting as a technical lead for customer IP products or energy-efficient AI inference/training accelerators is a significant asset.
- Proficiency with memory characterization and industry-standard EDA tools.
- Familiarity with scripting and automation (Perl, TCL, Python) is highly advantageous and will allow you to hit the ground running.
Company Description
As a trusted technology and capacity provider, TSMC is driven by the desire to be:
- The world's leading dedicated semiconductor foundry
- The technology leader with a strong reputation for manufacturing excellence
- Advancing semiconductor manufacturing innovations to enable the future of technology
TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world's leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry's leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.
For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC North America may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC North America obtaining any export license or other approval that may be required by the U.S. Government.
TSMC Core Values
At TSMC, we invite talented individuals who share our vision and values to contribute to our continued success. Our core values are the foundation of our culture, guiding every decision and action. We seek applicants who deeply resonate with these principles and embody them in their work:
- Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.
- Commitment: Employees are dedicated to the company, view the company's success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees.
- Innovation: Innovation is the wellspring of the Company's growth. It means more than new ideas; it means putting ideas into practice.
- Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term.
(For more details on TSMC's Core Values, please visit:https://www.tsmc.com/english/aboutTSMC/values)
Diversity statement
TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.
TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at g_accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC's obligations under applicable employment law. Reasonable accommodations will be determined on a case-by-case basis.
Pay Transparency / Benefits statement
At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $120,000 and $165,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC's total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.
Date: Jun 28, 2026
Country/Region: US
City: San Jose
Company: TSMC Technology, Inc.