MICROARCHITECT AND RTL DESIGN ENGINEER SANTA CLARA, CA About the role: We are seeking a seasoned ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
MICROARCHITECT AND RTL DESIGN ENGINEER SANTA CLARA, CA About the role: We are seeking a seasoned ... Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Develop memory hierarchies for high performance parallel computer architectures. (system-on-a-chip ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
ASIC Design Engineer
Santa Clara, CA · On-site
We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal ... Drive new memory system architectures from DRAM up.Explore architecture and feature trade-offs in ...
Product Design Engineer
San Jose, CA · On-site
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
Product Design Engineer
San Jose, CA · On-site
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
Senior VLSI CAD Engineer
Santa Clara, CA · Hybrid
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Senior VLSI CAD Engineer
Santa Clara, CA · Hybrid
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Product Design Engineer
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
Product Design Engineer
$120K - $300K/yr
... memory. We're pairing that intelligence with next-generation hardware to create a universal ... About the Role We're hiring a Product Design Engineer to help shape the physical form of our AI ...
As part of the GPU Memory Hierarchy Design team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day! As a GPU Design Engineer, you will ...
As part of the GPU Memory Hierarchy Design team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day! As a GPU Design Engineer, you will ...
Digital Design Engineer
Saratoga, CA · On-site
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
Saratoga, CA · On-site
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
$130K - $225K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Digital Design Engineer
Saratoga, CA · On-site
$150K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Quick apply
Digital Design Engineer
Saratoga, CA · On-site
$150K/yr
Design high-speed SERDES interfaces (PCIe, JESD, gigabit links) and DDR4/DDR5 memory interfaces ... Collaborate with FPGA engineers on support circuitry design, pinout planning, and power/layout ...
Senior VLSI CAD Engineer
Santa Clara, CA · On-site
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Senior VLSI CAD Engineer
Santa Clara, CA · On-site
$126K - $164K/yr
Join NVIDIA's custom RAM design team, where we are pushing the boundaries of memory technology to ... As a VLSI CAD Engineer, you will play a pivotal role in building the foundational tools and flows ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Staff Design Engineer
San Jose, CA · On-site
$145K - $246K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... As a Staff Design Engineer at Micron, you will play a pivotal role in highly technical teams! You ...
Principal Design Engineer
San Jose, CA · On-site
$176K - $298K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... The Principal Design Engineer in Micron's NVEG organization contributes to the development of new ...
Principal Design Engineer
San Jose, CA · On-site
$176K - $298K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... The Principal Design Engineer in Micron's NVEG organization contributes to the development of new ...
Design Engineer - Pathfinding Design
Folsom, CA · On-site
$86K - $171K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... You will support groups like Product Engineering, Test, Probe, Process Integration, Assembly, and ...
Design Engineer - Pathfinding Design
Folsom, CA · On-site
$86K - $171K/yr
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the ... You will support groups like Product Engineering, Test, Probe, Process Integration, Assembly, and ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... Bus fabric, especially APB/AHB/AXI, Memory systems, System debug architecture, Power management ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... Bus fabric, especially APB/AHB/AXI, Memory systems, System debug architecture, Power management ...
Memory Design Engineer information
See California salary details
$94.7K is the 25th percentile. Wages below this are outliers.
$79.4K - $98.3K
31% of jobs
$98.3K - $117.1K
5% of jobs
The median wage is $130.7K / yr.
$117.1K - $136K
19% of jobs
$150.5K is the 75th percentile. Wages above this are outliers.
$136K - $154.8K
26% of jobs
$154.8K - $173.7K
13% of jobs
$173.7K - $192.5K
4% of jobs
$192.5K - $211.3K
0% of jobs
$211.3K - $230.2K
0% of jobs
$230.2K - $249K
0% of jobs
$249K - $267.9K
1% of jobs
$267.9K - $286.7K
1% of jobs
$79.4K
$139.5K
$286.7K
How much do memory design engineer jobs pay per year?
As of Jun 10, 2026, the average yearly pay for memory design engineer in California is $139,500.00, according to ZipRecruiter salary data. Most workers in this role earn between $93,800.00 and $155,900.00 per year, depending on experience, location, and employer.
What are the primary challenges faced by Memory Design Engineers on a daily basis?
Memory Design Engineers often encounter challenges such as optimizing memory circuits for speed, power efficiency, and area while ensuring manufacturability and meeting reliability standards. Balancing these conflicting requirements requires strong analytical skills and close collaboration with verification, process, and layout teams. The role also involves troubleshooting design issues, staying updated with evolving semiconductor technologies, and ensuring timely project delivery. Overcoming these challenges fosters professional development and helps engineers build a solid track record in advanced technology nodes.
What are the key skills and qualifications needed to thrive in the Memory Design Engineer position, and why are they important?
A Memory Design Engineer requires a strong background in electrical engineering, semiconductor physics, and digital/analog circuit design, typically supported by a relevant bachelor's or master's degree. Expertise with EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages and memory characterization tools is essential. Strong problem-solving skills, attention to detail, and effective communication are important soft skills in this role. These competencies are crucial to ensure reliable, high-performance memory designs that meet rigorous industry standards and enable smooth collaboration within multidisciplinary engineering teams.
What is a Memory Design Engineer job?
A Memory Design Engineer is responsible for designing, developing, and optimizing memory circuits such as SRAM, DRAM, or flash memory. They work on transistor-level design, layout, simulation, and verification to ensure performance, power efficiency, and reliability. Engineers collaborate with process, verification, and product teams to meet design specifications and manufacturing constraints. Their role is critical in advancing memory technology for applications in consumer electronics, computing, and enterprise solutions.
What are the most commonly searched types of Memory Design Engineer jobs in California? The most popular types of Memory Design Engineer jobs in California are:
What are popular job titles related to Memory Design Engineer jobs in California? For Memory Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Memory Design Engineer jobs in California look for? The top searched job categories for Memory Design Engineer jobs in California are:
What cities in California are hiring for Memory Design Engineer jobs? Cities in California with the most Memory Design Engineer job openings:
Other
Posted 13 days ago
Job description
MICROARCHITECT AND RTL DESIGN ENGINEER
SANTA CLARA, CA
About the role:
We are seeking a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities:
Design and develop microarchitectures for a set of highly configurable IPs
Microarchitecture and RTL coding ensuring optimal performance, power, area
Collaborate with software teams to define configuration requirements, verification collaterals, etc.
Work with verification teams on assertions, test plans, debug, coverage, etc.
Qualifications and Preferred Skills:
BS, MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in microarchitecture and RTL development
Proficiency in Verilog, System Verilog
Familiarity with industry-standard EDA tools and methodologies
Experience with large high-speed, pipelined, stateful designs, and low power designs
In-depth understanding of on-chip interconnects and NoC's
Experience within Arm ACE/CHI or similar coherency protocols
Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's
Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
Experience with modern programming languages like Python is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills