ZipRecruiter

Log In

1

Mask Layout Designer Jobs (NOW HIRING)

Nvidia

Senior SRAM Layout Design Engineer

Durham, NC · Hybrid

Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM ... Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry ...

Texas Instruments

RET Layout/Mask Engineer

Dallas, TX · On-site

... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ... We offer competitive pay and benefits designed to help you and your family live your best life.

Apple

Digital Layout Design Engineer

Austin, TX · On-site

You will be part of an exciting silicon design group that is responsible for designing ... advanced CAD tools, mask design knowledge to layout corrections and robust physical design ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

You will be part of an exciting silicon design group that is responsible for designing ... advanced CAD tools, mask design knowledge to layout corrections and robust physical design ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

You will be part of an exciting silicon design group that is responsible for designing ... advanced CAD tools, mask design knowledge to layout corrections and robust physical design ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

You will be part of an exciting silicon design group that is responsible for designing ... advanced CAD tools, mask design knowledge to layout corrections and robust physical design ...

Apple

Digital Layout Design Engineer

Austin, TX

$137K - $250K/yr

You will be part of an exciting silicon design group that is responsible for designing ... advanced CAD tools, mask design knowledge to layout corrections and robust physical design ...

Texas Instruments

RET Layout/Mask Engineer

Dallas, TX · On-site

We offer competitive pay and benefits designed to help you and your family live your best life ... Layout/Mask design. Preferred qualifications: * Hands-on experience in design or PDK development ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

3D Glass Solutions, Inc-

CAD Engineer

Albuquerque, NM · On-site

Support the creation of internal standards and tools for lithography mask layout and other CAD ... Work directly and independently with customers to iterate on designs, refining them for successful ...

Apply Early

3D Glass Solutions

CAD Engineer

Albuquerque, NM

Support the creation of internal standards and tools for lithography mask layout and other CAD ... Work directly and independently with customers to iterate on designs, refining them for successful ...

3D Glass Solutions

CAD Engineer

Albuquerque, NM · On-site

... mask layout and other CAD applications. • Partner with Project Field Application Engineers and ... on designs, refining them for successful fabrication. • Support pre-fabrication processes ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

next page

Showing results 1-20

All JobsMask Layout Designer Jobs

Mask Layout Designer information

See salary details

$10

$41

$100

How much do mask layout designer jobs pay per hour?

As of Jul 4, 2026, the average hourly pay for mask layout designer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What are mask layout designers?

Mask layout designers are professionals who create the detailed physical layouts for integrated circuits (ICs) or semiconductor devices. They translate circuit schematics into precise geometric patterns that define how components and connections will be fabricated on silicon chips. Their work involves using specialized software tools to optimize the arrangement for performance, manufacturability, and adherence to design rules. Mask layout designers play a crucial role in ensuring that electronic devices function correctly and efficiently.

What are the key skills and qualifications needed to thrive as a Mask Layout Designer, and why are they important?

To thrive as a Mask Layout Designer, you need a solid understanding of semiconductor physics, IC design principles, and experience with layout design rules, usually supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, as well as knowledge of DRC/LVS verification processes, is essential. Attention to detail, problem-solving, and effective collaboration with design and verification teams are valuable soft skills. These competencies ensure the creation of accurate, manufacturable layouts that meet stringent specifications, directly impacting chip performance and yield.

What is the difference between Mask Layout Designer vs IC Design Engineer?

AspectMask Layout DesignerIC Design Engineer
Primary FocusDesigning photomask layouts for semiconductor manufacturingDesigning integrated circuit architectures and circuit components
Skills & CertificationsKnowledge of mask design tools, semiconductor fabrication processesStrong circuit theory, EDA tools, and semiconductor device knowledge
Work EnvironmentSemiconductor fabrication facilities, design labsDesign offices, R&D labs, semiconductor companies
Industry UsageUsed in photomask manufacturing for chip productionUsed in chip and circuit development for various electronic devices

While both roles are integral to semiconductor development, the Mask Layout Designer focuses on creating precise photomask patterns for manufacturing, whereas the IC Design Engineer develops the overall circuit architecture and logic. Understanding these distinctions helps professionals and employers align skills and expectations in the semiconductor industry.

What are some common challenges faced by Mask Layout Designers when collaborating with circuit design engineers?

One common challenge Mask Layout Designers face is translating circuit schematics into efficient and manufacturable layouts while ensuring all design rules and constraints are met. Effective communication is crucial, as discrepancies between layout and circuit intent can arise, requiring iterative feedback and close coordination with circuit design engineers. Additionally, balancing performance, area, and manufacturability often involves trade-offs, making teamwork and proactive problem-solving essential parts of the role.
More about Mask Layout Designer jobs
What cities are hiring for Mask Layout Designer jobs? Cities with the most Mask Layout Designer job openings:
What states have the most Mask Layout Designer jobs? States with the most job openings for Mask Layout Designer jobs include:
What job categories do people searching Mask Layout Designer jobs look for? The top searched job categories for Mask Layout Designer jobs are:
Mask Layout Designer jobs near you
Senior SRAM Layout Design Engineer

Senior SRAM Layout Design Engineer

Nvidia Corporation

Santa Clara, CA • On-site

Full-time

Posted 22 days ago

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, working closely with circuit design, physical design, integration, CAD, and foundry teams. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
What you will be doing:
  • Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
  • Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
  • Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
  • Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
  • Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
  • Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
  • Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
  • Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
  • Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.

What we need to see:
  • Have a BSEE or equivalent experience
  • 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
  • Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
  • Solid grasp of SRAM and memory layout principles.
  • Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
  • Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
  • Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
  • Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
  • Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
  • Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.

Ways to stand out from the crowd:
  • Experience in scripting using Cadence SKILL, Python, or comparable languages for layout automation, checks, reporting, or improving workflows.
  • Strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing closure at both IP and top level.

Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Nvidia logo

About Nvidia

Sourced by ZipRecruiter

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1993

View All Nvidia Jobs

Apply