RFIC Layout Engineer
Irvine, CA · On-site
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
Irvine, CA · On-site
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
Irvine, CA · On-site
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
Irvine, CA · On-site
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
Contribute to the product concept phase by delivering preliminary substrate designs and ... Minimum 3-5 years of experience in IC package layout design. * Proficient with Allegro X APD.
New
Contribute to the product concept phase by delivering preliminary substrate designs and ... Minimum 3-5 years of experience in IC package layout design. * Proficient with Allegro X APD.
New
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
RFIC Layout Engineer
$137K - $250K/yr
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems. Excellent communication skills and ability to ...
Substrate/Package Layout Engineer
$141K - $226K/yr
Peer reviews of substrate/package designs is also an important element of the role. You will work with substrate/package vendors to define layout/panel/stack-up design and other specifications. In ...
Substrate/Package Layout Engineer
$141K - $226K/yr
Peer reviews of substrate/package designs is also an important element of the role. You will work with substrate/package vendors to define layout/panel/stack-up design and other specifications. In ...
About You and The Role Zipline designs, manufactures, and operates autonomous delivery systems that ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
Quick apply
About You and The Role Zipline designs, manufactures, and operates autonomous delivery systems that ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
Substrate/Package Layout Engineer
San Jose, CA · On-site
$141K - $226K/yr
Peer reviews of substrate/package designs is also an important element of the role. You will work with substrate/package vendors to define layout/panel/stack-up design and other specifications. In ...
Substrate/Package Layout Engineer
San Jose, CA · On-site
$141K - $226K/yr
Peer reviews of substrate/package designs is also an important element of the role. You will work with substrate/package vendors to define layout/panel/stack-up design and other specifications. In ...
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
Contribute to the product concept phase by delivering preliminary substrate designs and ... Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout, Altium, etc.
Package Layout Engineer
Mountain View, CA · On-site
$157K - $176K/yr
Contribute to the product concept phase by delivering preliminary substrate designs and ... Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout, Altium, etc.
Staff Custom Analog Layout Engineer
San Jose, CA · On-site
$139K - $258K/yr
The successful candidate shall work closely with circuit designers to generate high-quality layout in a highly efficient way. He or she shall utilize advanced CAD tools and mask design knowledge to ...
Staff Custom Analog Layout Engineer
San Jose, CA · On-site
$139K - $258K/yr
The successful candidate shall work closely with circuit designers to generate high-quality layout in a highly efficient way. He or she shall utilize advanced CAD tools and mask design knowledge to ...
Sr. ASIC Layout Design Engineer
Goleta, CA · On-site
$113K - $151K/yr
Collaborate with circuit designers to optimize floor-planning, placement, and routing. * Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout ...
Sr. ASIC Layout Design Engineer
Goleta, CA · On-site
$113K - $151K/yr
Collaborate with circuit designers to optimize floor-planning, placement, and routing. * Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout ...
High Speed Photonic Integrated Circuit Designer
Gardena, CA · On-site
$160K - $190K/yr
Drive photonic tape-outs end-to-end, including circuit design, DOE planning, hands-on layout ... Analyze measurement results (e.g., EO S-parameters/S21, eye diagrams, mask margin, RIN, chirp) and ...
High Speed Photonic Integrated Circuit Designer
Gardena, CA · On-site
$160K - $190K/yr
Drive photonic tape-outs end-to-end, including circuit design, DOE planning, hands-on layout ... Analyze measurement results (e.g., EO S-parameters/S21, eye diagrams, mask margin, RIN, chirp) and ...
High Speed Photonic Integrated Circuit Designer
$160K - $190K/yr
Drive photonic tape-outs end-to-end, including circuit design, DOE planning, hands-on layout ... Analyze measurement results (e.g., EO S-parameters/S21, eye diagrams, mask margin, RIN, chirp) and ...
High Speed Photonic Integrated Circuit Designer
$160K - $190K/yr
Drive photonic tape-outs end-to-end, including circuit design, DOE planning, hands-on layout ... Analyze measurement results (e.g., EO S-parameters/S21, eye diagrams, mask margin, RIN, chirp) and ...
Sr. ASIC Layout Design Engineer
Goleta, CA · On-site
$113K - $151K/yr
Collaborate with circuit designers to optimize floor-planning, placement, and routing. * Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout ...
Sr. ASIC Layout Design Engineer
Goleta, CA · On-site
$113K - $151K/yr
Collaborate with circuit designers to optimize floor-planning, placement, and routing. * Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
... compatibility studies, and mask layout CAD * Conceptual contributions to bulk material ... Designing, coordinating, and conducting experiments in various user facilities * Contribution to ...
Process Engineer
San Francisco, CA · On-site
$150K - $250K/yr
... compatibility studies, and mask layout CAD * Conceptual contributions to bulk material ... Designing, coordinating, and conducting experiments in various user facilities * Contribution to ...
The successful candidate shall work closely with circuit designers to generate high-quality layout in a highly efficient way. He or she shall utilize advanced CAD tools and mask design knowledge to ...
The successful candidate shall work closely with circuit designers to generate high-quality layout in a highly efficient way. He or she shall utilize advanced CAD tools and mask design knowledge to ...
Mask Layout Designer information
See California salary details
$16.57 is the 25th percentile. Wages below this are outliers.
$9.96 - $18.12
31% of jobs
$18.12 - $26.27
16% of jobs
The median wage is $28.71 / hr.
$26.27 - $34.42
11% of jobs
$34.42 - $42.57
15% of jobs
$47.67 is the 75th percentile. Wages above this are outliers.
$42.57 - $50.73
4% of jobs
$50.73 - $58.88
6% of jobs
$58.88 - $67.03
5% of jobs
$67.03 - $75.18
3% of jobs
$75.18 - $83.33
2% of jobs
$83.33 - $91.49
3% of jobs
$91.49 - $99.64
3% of jobs
$9
$40
$99
How much do mask layout designer jobs pay per hour?
As of Aug 23, 2026, the average hourly pay for mask layout designer in California is $40.76, according to ZipRecruiter salary data. Most workers in this role earn between $17.31 and $57.64 per hour, depending on experience, location, and employer.
What is a mask layout designer?
Mask layout designers are professionals who create the detailed physical layouts for integrated circuits (ICs) or semiconductor devices. They translate circuit schematics into precise geometric patterns that define how components and connections will be fabricated on silicon chips. Their work involves using specialized software tools to optimize the arrangement for performance, manufacturability, and adherence to design rules. Mask layout designers play a crucial role in ensuring that electronic devices function correctly and efficiently.
What are the key skills and qualifications needed to thrive as a mask layout designer?
To thrive as a Mask Layout Designer, you need a solid understanding of semiconductor physics, IC design principles, and experience with layout design rules, usually supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys, as well as knowledge of DRC/LVS verification processes, is essential. Attention to detail, problem-solving, and effective collaboration with design and verification teams are valuable soft skills. These competencies ensure the creation of accurate, manufacturable layouts that meet stringent specifications, directly impacting chip performance and yield.
What are some common challenges faced by mask layout designers when collaborating with circuit design engineers?
One common challenge Mask Layout Designers face is translating circuit schematics into efficient and manufacturable layouts while ensuring all design rules and constraints are met. Effective communication is crucial, as discrepancies between layout and circuit intent can arise, requiring iterative feedback and close coordination with circuit design engineers. Additionally, balancing performance, area, and manufacturability often involves trade-offs, making teamwork and proactive problem-solving essential parts of the role.
What is the difference between Mask Layout Designer vs IC Design Engineer?
| Aspect | Mask Layout Designer | IC Design Engineer |
|---|---|---|
| Primary Focus | Designing photomask layouts for semiconductor manufacturing | Designing integrated circuit architectures and circuit components |
| Skills & Certifications | Knowledge of mask design tools, semiconductor fabrication processes | Strong circuit theory, EDA tools, and semiconductor device knowledge |
| Work Environment | Semiconductor fabrication facilities, design labs | Design offices, R&D labs, semiconductor companies |
| Industry Usage | Used in photomask manufacturing for chip production | Used in chip and circuit development for various electronic devices |
While both roles are integral to semiconductor development, the Mask Layout Designer focuses on creating precise photomask patterns for manufacturing, whereas the IC Design Engineer develops the overall circuit architecture and logic. Understanding these distinctions helps professionals and employers align skills and expectations in the semiconductor industry.
What are popular job titles related to Mask Layout Designer jobs in California?
For Mask Layout Designer jobs in California, the most frequently searched job titles are:
What job categories do people searching Mask Layout Designer jobs in California look for?
The top searched job categories for Mask Layout Designer jobs in California are:
What cities in California are hiring for Mask Layout Designer jobs?
Cities in California with the most Mask Layout Designer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what's considered feasible? As part of an outstanding `team, you'll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You'll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you'll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you'll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide.
Description
Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.
- Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
- Co-work with designers on block-level and top-level floorplanning.
- Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
- Top-level layout integration and verification, schedule management.
Minimum Qualifications
BS and 3+ years of relevant industry experience.
Good understanding of RC delay, electromigration, and coupling.
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience).
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems.
Excellent communication skills and ability to work with multi-functional teams.
Preferred Qualifications
Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing.
Solid understanding of RC delay, electromigration, and coupling.
Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology.
Capability to lead other layout engineers for top-level integration.
Scripting skills in PERL or SKILL are a plus.
Extensive knowledge of CADENCE layout tools.
Description
Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.
- Block level and top-level layout through full verification flow, including extraction, DRC, LVS, and DFM checking.
- Co-work with designers on block-level and top-level floorplanning.
- Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.
- Top-level layout integration and verification, schedule management.
Minimum Qualifications
BS and 3+ years of relevant industry experience.
Good understanding of RC delay, electromigration, and coupling.
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (16nm and lower with FinFet experience).
Ability to recognize failure-prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems.
Excellent communication skills and ability to work with multi-functional teams.
Preferred Qualifications
Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high-frequency routing.
Solid understanding of RC delay, electromigration, and coupling.
Understanding of guard rings, DNW, PN junctions, and sophisticated process effects such as LOD, WPE, etc.
High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology.
Capability to lead other layout engineers for top-level integration.
Scripting skills in PERL or SKILL are a plus.
Extensive knowledge of CADENCE layout tools.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976