All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...
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Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...
RF/Analog Mixed Signal Design Engineer
$129K - $225K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
RF/Analog Mixed Signal Design Engineer
$129K - $225K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Our engineers are working at the leading edge of computational lithography, Resolution Enhancement ... Use design rules and/or existing layouts to create/modify test features. * Maintain a list of ...
Our engineers are working at the leading edge of computational lithography, Resolution Enhancement ... Use design rules and/or existing layouts to create/modify test features. * Maintain a list of ...
PLL Design Engineer
$129K - $225K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$129K - $225K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$184K - $324K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$184K - $324K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
RF/Analog Mixed Signal Design Engineer
$184K - $324K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
RF/Analog Mixed Signal Design Engineer
$184K - $324K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
Analog IC Design Engineer, High-Speed
Mountain View, CA · On-site
$238K/yr
As a member of the analog team, you'll collaborate with our architects and engineers to develop ... Drive block-level floorplan, mask design views, and their reviews * Run post-layout and mixed ...
Analog IC Design Engineer, High-Speed
Mountain View, CA · On-site
$238K/yr
As a member of the analog team, you'll collaborate with our architects and engineers to develop ... Drive block-level floorplan, mask design views, and their reviews * Run post-layout and mixed ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
PIC Engineering Reports to: Senior Director, PIC Engineering About Us Quantum Computing Inc. (QCi ... Drive process integration efforts including mask design, fabrication flow development, and ...
PIC Engineering Reports to: Senior Director, PIC Engineering About Us Quantum Computing Inc. (QCi ... Drive process integration efforts including mask design, fabrication flow development, and ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Senior Principal Engineer, Photonics Design Location : Hoboken, NJ/Cranbury, NJ Division ... Drive process integration efforts including mask design, fabrication flow development, and ...
Senior Principal Engineer, Photonics Design Location : Hoboken, NJ/Cranbury, NJ Division ... Drive process integration efforts including mask design, fabrication flow development, and ...
PIC Engineering Reports to: Senior Director, PIC Engineering About Us Quantum Computing Inc. (QCi ... Drive process integration efforts including mask design, fabrication flow development, and ...
PIC Engineering Reports to: Senior Director, PIC Engineering About Us Quantum Computing Inc. (QCi ... Drive process integration efforts including mask design, fabrication flow development, and ...
ROIC Design Engineer Principal
Goleta, CA · On-site
... mask design • Serial interface designs including serial peripheral, I2C, and other standard ... of engineering teams over product lifecycles • Understanding of IR sensor systems and all of ...
ROIC Design Engineer Principal
Goleta, CA · On-site
... mask design • Serial interface designs including serial peripheral, I2C, and other standard ... of engineering teams over product lifecycles • Understanding of IR sensor systems and all of ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering Required. Preferred ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering Required. Preferred ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
MASK Design Engineer information
See salary details
$45K - $57.8K
4% of jobs
$57.8K - $70.5K
2% of jobs
$70.5K - $83.3K
12% of jobs
$93.7K is the 25th percentile. Wages below this are outliers.
$83.3K - $96.1K
9% of jobs
$96.1K - $108.9K
11% of jobs
The median wage is $120.7K / yr.
$108.9K - $121.6K
14% of jobs
$121.6K - $134.4K
22% of jobs
$136.8K is the 75th percentile. Wages above this are outliers.
$134.4K - $147.2K
9% of jobs
$147.2K - $160K
9% of jobs
$160K - $172.7K
3% of jobs
$172.7K - $185.5K
6% of jobs
$45K
$120.8K
$185.5K
How much do mask design engineer jobs pay per year?
What is a mask design engineer?
What are some common challenges faced by Mask Design Engineers during the IC layout process?
What is the difference between Mask Design Engineer vs Photomask Fabrication Engineer?
| Aspect | Mask Design Engineer | Photomask Fabrication Engineer |
|---|---|---|
| Primary Role | Designs photomasks used in semiconductor manufacturing | Manufactures and inspects photomasks based on design specifications |
| Skills & Certifications | Knowledge of CAD tools, semiconductor processes, optical design | Experience with lithography, cleanroom protocols, quality control |
| Work Environment | Design labs, CAD rooms, collaboration with chip designers | Cleanrooms, fabrication facilities, equipment operation |
| Industry Usage | Used in semiconductor and electronics manufacturing | Used in photomask production for chip fabrication |
While both roles are essential in semiconductor manufacturing, the Mask Design Engineer focuses on creating the design files for photomasks, whereas the Photomask Fabrication Engineer handles the physical production and quality control of these masks. Both positions require specialized skills and work closely within the same industry but serve different stages of the mask creation process.
What are the key skills and qualifications needed to thrive as a Mask Design Engineer, and why are they important?
What are Mask Design Engineers?
How much does a mask design engineer make at Nvidia?
What is the highest paid design job?
What's a design engineer's salary?

Full-time
Medical, Dental, Vision, Life, Retirement
Posted 13 days ago
Job description
- All tasks related to mask design and layout of photonic integrated circuits
- Creating mask designs in conjunction with optical designers and process engineers.
- Creating design rules and implementing within layout software.
- Leading tape-out process for photonic device designs in conjunction with optical designers and process engineers.
- Expanding photonic element library within CAD software
- Organizing and tracking all versions of design layouts.
- Maintaining database of existing mask sets
Requirements
- B.S. (M.S. preferred) in Electrical Engineering, or a closely related field
- At least five (5) years of work experience in photonic IC layout & design
- Experience with commercial foundry tape-out process
- Experience with commercial layout software (Cadence, dw-2000, Mentor Graphics)
- Deep understanding of DRC rules and their creation.
- Strong problem solving and critical thinking skills.
- Strong communication, presentation and documentation skills
- Must be able to work effectively in a dynamic start-up environment.
Why Skorpios?
At Skorpios, you will be at the forefront of the silicon photonics revolution. We offer the chance to work on truly disruptive technology that is changing how the world connects. You will be part of a team where technical excellence is celebrated and where your contributions have a direct impact on the success of our next-generation product lines. Skorpios offers an excellent benefits package which includes:
- Competitive salary
- Medical
- Dental
- Vision
- 401(k)
- Company paid life insurance
- Company paid disability
- Paid holidays
- Gym Membership Discounts
Export Control / ITAR Statement: "This position is located at a facility that operates under International Traffic in Arms Regulations (ITAR). All applicants must be 'U.S. persons' within the meaning of ITAR. ITAR defines a 'U.S. person' as a U.S. Citizen, U.S. Permanent Resident (i.e., 'Green Card Holder'), Political Asylee, or Refugee."
Skorpios Technologies, Inc. is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, national origin, ancestry, age (40 and over), physical or mental disability, medical condition, genetic information, marital status, military or veteran status, protected leave status, or any other characteristic protected by applicable federal, state, or local laws.
As a federal contractor, Skorpios Technologies, Inc. takes affirmative action to employ and advance in employment qualified minorities, women, protected veterans, and individuals with disabilities. We encourage all qualified candidates to apply.
Skorpios Technologies, Inc. is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may contact us at or AskHR@Skorpiosinc.com.
About Skorpios Technologies
Sourced by ZipRecruiter
Industry
Telecommunications
Company size
11 - 50 Employees
Headquarters location
Albuquerque, NM, US
Year founded
2009