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Mask Design Engineer Jobs in Phoenix, AZ (NOW HIRING)

As a Mask Layout Designer, you will have the opportunity to work with a team of layout designers, and design, process integration, and package engineers developing high quality Power MOSFETS for ...

As a Mask Layout Designer, you will have the opportunity to work with a team of layout designers, and design, process integration, and package engineers developing high quality Power MOSFETS for ...

Support endtoend systems analysis and contribute to the design of RF and mixedsignal communications ... masks, hearing protectors, heel/wrist straps and any other required PPE * May be exposed to unusual ...

Support end-to-end systems analysis and contribute to the design of RF and mixed-signal ... masks, hearing protectors, heel/wrist straps and any other required PPE * May be exposed to unusual ...

Lead Data Engineer

Phoenix, AZ · On-site

$113.70K - $136.50K/yr

Design and lead scalable data architecture aligned with business strategy * Build and optimize real ... Deep expertise in Snowflake , including medallion architecture, Snowpipe, RBAC, and data masking

Solid understanding of prompt engineering frameworks and design patterns. * Hands-on experience ... Enforce data privacy, PII masking, and access control in AI workflows. * Collaborate with Risk ...

Senior Data & AI Engineer

Phoenix, AZ · On-site +1

$50 - $60/hr

Your role · Design, implement, and optimize data platforms using Snowflake and Microsoft Fabric ... masking, tokenization, and de-identification. · Create conceptual, logical, and physical data ...

We are seeking a highly skilled Prompt Engineering & AI Solutions Specialist to design, develop ... PII masking, and access control in AI workflows. • Collaborate with Risk, Legal, and Compliance ...

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Process Engineer (Etch)

Chandler, AZ · On-site

$75K - $110K/yr

Perform Design of Experiments (DOE) to optimize process windows and stability * Manage lifecycle of ... Troubleshoot etch issues such as non-uniformity, residue formation, micro-masking, and particle ...

Network Security Engineer

Phoenix, AZ

$103.80K - $142K/yr

We work every single day to design and manufacture silicon products that empower people's digital ... Expert in TCP/IP variable length subnet masking, address allocation in both V4/V6. * Ability to ...

Network Security Engineer

Phoenix, AZ · On-site

$103.80K - $142K/yr

We work every single day to design and manufacture silicon products that empower people's digital ... Expert in TCP/IP variable length subnet masking, address allocation in both V4/V6. * Ability to ...

Test Data Engineer

Phoenix, AZ · On-site

$55 - $60/hr

Design, write, and execute SQL queries to prepare manual test datasets. * Work closely with QA and ... Implement data masking, anonymization, and synthetic data generation as required. * Maintain ...

Controls Engineer 1

Phoenix, AZ · On-site

$79.70K - $103.10K/yr

Responsibilities: apply standard engineering techniques to design, develop and maintain ... mask, cleanroom suit). * Approximately 80/20 office and shop floor environment. * Low noise levels ...

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Mask Design Engineer information

See Phoenix, AZ salary details

$44.7K

$120K

$184.2K

How much do mask design engineer jobs pay per year?

As of May 27, 2026, the average yearly pay for mask design engineer in Phoenix, AZ is $119,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $89,400.00 and $143,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Mask Design Engineer, and why are they important?

To thrive as a Mask Design Engineer, you need expertise in semiconductor device physics, layout design, and photolithography, typically supported by a degree in electrical engineering or a related field. Familiarity with CAD tools such as Cadence Virtuoso, Calibre, and other EDA software, as well as knowledge of industry standards like DRC/LVS checks, is essential. Attention to detail, problem-solving skills, and effective communication help ensure accuracy and collaboration within engineering teams. These skills and qualifications are critical for producing precise mask layouts that enable successful chip fabrication and yield.

What are some common challenges faced by Mask Design Engineers during the IC layout process?

Mask Design Engineers often encounter challenges such as adhering to strict design rules while maximizing layout efficiency and yield. They must manage complex design data, collaborate closely with circuit designers to implement feedback, and ensure that the mask layouts are optimized for both manufacturability and performance. Additionally, keeping up with evolving technology nodes and lithography constraints requires continuous learning and adaptation. Effective communication and attention to detail are crucial for overcoming these challenges and delivering high-quality mask designs on tight schedules.

What are Mask Design Engineers?

Mask Design Engineers are specialized professionals who create photomasks used in the fabrication of semiconductor devices. They use advanced computer-aided design (CAD) tools to translate circuit layouts into precise patterns that guide the manufacturing of microchips. These engineers work closely with circuit designers and fabrication teams to ensure accuracy and efficiency in chip production. Their expertise is crucial for achieving the high levels of miniaturization and performance required in modern electronics.

What is the difference between Mask Design Engineer vs Photomask Fabrication Engineer?

AspectMask Design EngineerPhotomask Fabrication Engineer
Primary RoleDesigns photomasks used in semiconductor manufacturingManufactures and inspects photomasks based on design specifications
Skills & CertificationsKnowledge of CAD tools, semiconductor processes, optical designExperience with lithography, cleanroom protocols, quality control
Work EnvironmentDesign labs, CAD rooms, collaboration with chip designersCleanrooms, fabrication facilities, equipment operation
Industry UsageUsed in semiconductor and electronics manufacturingUsed in photomask production for chip fabrication

While both roles are essential in semiconductor manufacturing, the Mask Design Engineer focuses on creating the design files for photomasks, whereas the Photomask Fabrication Engineer handles the physical production and quality control of these masks. Both positions require specialized skills and work closely within the same industry but serve different stages of the mask creation process.

Infographic showing various Mask Design Engineer job openings in Phoenix, AZ as of May 2026, with employment types broken down into 92% Full Time, and 8% Contract. Highlights an 92% In-person, and 8% Remote job distribution, with an average salary of $119,992 per year, or $57.7 per hour.
CAD Layout Engineer

CAD Layout Engineer

onsemi

Scottsdale, AZ

Full-time

Posted 23 days ago


Onsemi rating

8.0

Company rating: 8.0 out of 10

Based on 18 frontline employees who took The Breakroom Quiz


Job description

Job Summary: 

The Power Solutions Group (PSG) MOSFET division of onsemi is seeking a Mask Layout Designer who is self-driven and motivated to join their Discrete Power MOSFET Team. As a Mask Layout Designer, you will have the opportunity to work with a team of layout designers, and design, process integration, and package engineers developing high quality Power MOSFETS for discrete products and modules. This position needs a person at a minimum with a background and use of CAD layout software (preferably Cadence). Not inclusive but preferably its application to layout of discrete power products. Here at onsemi we have a great culture of teamwork in an environment to innovate and design industry leading technology.  At onsemi our design team is dedicated to meeting the demands of delivering leading edge technologies and value added products to customers.


 

onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world's most complex challenges and leads the way in creating a safer, cleaner, and smarter world.

More details about our company benefits can be found here:

https://www.onsemi.com/careers/career-benefits

We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.


onsemi is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, ethnicity, color, religion, ancestry, national origin, age, marital status, pregnancy, sex, sexual orientation, physical or mental disability, medical condition, genetic information, military or veteran status, gender identity, gender expression, or any other protected category under applicable federal, state, or local laws.

If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Talent.acquisition@onsemi.com for assistance.

Requirements: 

  • Associate degree or BS degree in electronics with preferably two or more years experience in industry doing layout.
  • Working aptitude for CAD-based design layout software. Proficiency using Cadence Virtuoso is highly desired.
  • Demonstrated ability to pay a high attention to detail, to ask clear questions for details, and to produce first-time-error free layouts.
  • Good personal skills, willing to work with teams across many geographic locations.
  • Experience in discrete Power MOSFET layout is a "Plus".
  • Knowledge of "AutoCad" and "Calibre Mask Data Prep Viewer" is a "Plus".
  • Fluency in the English language.
  • Able to work with a group of engineers inside and outside of the country across multiple time zones.
  • Ability to be mentored by and help others learn in a positive team development roll.


 

  • Perform physical design (layout) of discrete power MOSFETs
  • Generate verification (DRC), debug using the Calibre CAD tool, and job deck reviews.
  • Interface with design, process integration, and package engineers to find optimal layout design solutions for discrete and module power MOSFET's
  • Follow New Product Development (NPD) and Technology Development (TD) workflows and documentation procedures.
  • Understand how to generate and validate layouts using DRCs.
  • Be coachable in coming up to speed and contributing to current workflows and help improve efficiency.
  • Participate and support team members in their work and production needs.
  • Manage your work to accomplish the tasks needed for maintaining product & technology development schedules.
  • Provide technical expertise, guidance, and support to other team members where possible.
  • Communicate detailed information needed for quality work throughout the production cycle.

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