... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
... Engineering, or related field with 4+ years of industry experience In addition, all candidates must have: * Expert-level proficiency in Verilog / SystemVerilog (RTL design) * Digital logic ...
Electrologixs experience in hardware design and application logic design , with hands‑on exposure to ACE, AutoCAD, and MicroStation. Job Summary We are seeking a skilled Electrical Design Engineer ...
Quick apply
Electrologixs experience in hardware design and application logic design , with hands‑on exposure to ACE, AutoCAD, and MicroStation. Job Summary We are seeking a skilled Electrical Design Engineer ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
Santa Clara, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off-chip interconnect network, MP coherency ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127.20 - $190.80/hr
Overview Qualcomm Technologies, Inc. is seeking a design-focused engineer to contribute to the next generation of microarchitecture and logic for the Hexagon NPU, supporting a wide range of AI/ML ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127.20 - $190.80/hr
Overview Qualcomm Technologies, Inc. is seeking a design-focused engineer to contribute to the next generation of microarchitecture and logic for the Hexagon NPU, supporting a wide range of AI/ML ...
Mixed Signal Logic Design Engineer
San Jose, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
San Jose, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal ... Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Job Area: Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next‑generation microarchitecture and logic for Qualcomm ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Job Area: Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next‑generation microarchitecture and logic for Qualcomm ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU ...
New
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU ...
New
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU ...
Physical Design Engineer
Beaverton, OR · On-site
$141K - $145K/yr
... logic design teams, with a critical impact on delivering outstanding PHY designs. You will be ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...
Physical Design Engineer
Beaverton, OR · On-site
$141K - $145K/yr
... logic design teams, with a critical impact on delivering outstanding PHY designs. You will be ... Description As a Physical Design engineer you will contribute to all phases of physical design of ...
Logic Design Engineer information
See salary details
$18.03 - $23.08
1% of jobs
$23.08 - $28.13
2% of jobs
$28.13 - $33.17
7% of jobs
$33.17 - $38.22
11% of jobs
$39.68 is the 25th percentile. Wages below this are outliers.
$38.22 - $43.27
14% of jobs
$43.27 - $48.32
15% of jobs
The median wage is $48.51 / hr.
$48.32 - $53.37
14% of jobs
$53.37 - $58.41
8% of jobs
$59.90 is the 75th percentile. Wages above this are outliers.
$58.41 - $63.46
12% of jobs
$63.46 - $68.51
12% of jobs
$68.51 - $73.56
5% of jobs
$18
$50
$73
How much do logic design engineer jobs pay per hour?
As of Aug 17, 2026, the average hourly pay for logic design engineer in the United States is $50.69, according to ZipRecruiter salary data. Most workers in this role earn between $39.18 and $61.78 per hour, depending on experience, location, and employer.
What is a logic design engineer?
A Logic Design Engineer is a professional who designs and develops digital circuits and systems, focusing on the logical function and behavior of hardware components. Their main responsibility is to translate high-level requirements into detailed logic circuits using hardware description languages like VHDL or Verilog. Logic Design Engineers work closely with system architects, verification teams, and physical design engineers to ensure that the digital systems meet specifications and function correctly. Their work is crucial in industries such as semiconductor, computing, and consumer electronics, where they help create chips, processors, and other digital devices.
How does a logic design engineer typically collaborate with software and hardware teams during a project?
Logic Design Engineers frequently work closely with both software and hardware teams throughout the product development cycle. They often interface with hardware engineers to ensure that the logic designs are compatible with physical constraints and meet performance requirements. Additionally, they collaborate with software engineers to verify that the designed logic meets system-level functionality and integrates smoothly with firmware or embedded software. Effective communication and iterative feedback are key, as specifications and requirements may evolve during the project.
What are the key skills and qualifications needed to thrive as a logic design engineer, and why are they important?
To thrive as a Logic Design Engineer, you need a solid background in digital design, computer architecture, and proficiency in hardware description languages such as VHDL or Verilog, usually supported by a degree in electrical or computer engineering. Experience with simulation tools, synthesis tools, and FPGA or ASIC design flows, as well as familiarity with industry-standard EDA software, is essential. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set outstanding engineers apart. These competencies ensure the accurate and efficient development of complex digital systems, meeting project requirements and industry standards.
What is the difference between Logic Design Engineer vs Digital Design Engineer?
| Aspect | Logic Design Engineer | Digital Design Engineer |
|---|---|---|
| Primary Focus | Designing and developing digital logic circuits and systems | Designing complete digital systems, including hardware and firmware integration |
| Skills & Certifications | Digital logic, HDL (VHDL/Verilog), FPGA/ASIC design | Digital logic, HDL, FPGA/ASIC, embedded systems |
| Work Environment | Semiconductor companies, hardware firms, R&D labs | Electronics manufacturers, integrated circuit companies, tech firms |
| Industry Usage | Commonly used in chip design and hardware development | Used in designing complete digital products and systems |
While both roles involve digital logic and HDL skills, a Logic Design Engineer primarily focuses on creating digital logic circuits, whereas a Digital Design Engineer works on designing entire digital systems, often integrating hardware and firmware. The roles overlap but differ in scope and application.
More about Logic Design Engineer jobs
What cities are hiring for Logic Design Engineer jobs?
Cities with the most Logic Design Engineer job openings:
What states have the most Logic Design Engineer jobs?
States with the most job openings for Logic Design Engineer jobs include:
What job categories do people searching Logic Design Engineer jobs look for?
The top searched job categories for Logic Design Engineer jobs are:
Full-time
Medical, Retirement, PTO
Re-posted 15 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 157 rated electronics manufacturers
Job description
Job Details:
Job Description:
Position Overview
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Key Responsibilities
What We're Looking For
To be successful in this role, you should demonstrate the following professional traits:
Qualifications:
Minimum Qualifications
You must possess one of the following education and experience combinations to be initially considered for this position:
In addition, all candidates must have:
Preferred Qualifications
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Description:
Position Overview
Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.
Key Responsibilities
- Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems
- Participate in the definition of architecture and microarchitecture features of the block being designed
- Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation
- Write and optimize mixed-signal logic to meet power, performance, area, and timing goals
- Ensure design integrity for physical implementation
- Review verification plans and implementation to confirm design features are verified correctly
- Resolve and implement corrective measures for failing RTL tests to ensure feature correctness
- Support SoC customers to ensure high-quality integration of the IP block
What We're Looking For
To be successful in this role, you should demonstrate the following professional traits:
- Cross-functional collaboration - ability to work effectively with analog, digital, and physical design teams throughout the design cycle
- Ownership mentality - capable of independently designing and owning mixed-signal subsystems and IP blocks end-to-end
- Strong debugging instincts - skilled at identifying and resolving issues across both analog and digital domains with precision and efficiency
Qualifications:
Minimum Qualifications
You must possess one of the following education and experience combinations to be initially considered for this position:
- Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 7+ years of industry experience, OR
- Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 4+ years of industry experience
In addition, all candidates must have:
- Expert-level proficiency in Verilog / SystemVerilog (RTL design)
- Digital logic fundamentals
- Experience integrating analog IP with digital logic
- Deep knowledge of RTL-to-GDSII flow, STA, and CDC
- Familiarity with EDA tools
- Understanding of timing, power, and performance trade-offs
Preferred Qualifications
- Knowledge of Power Delivery and Power Management systems
- Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators
- DFT as it relates to mixed-signal HIP
- Scripting language experience, including Perl, TCL/Tk, or Python
- Experience with mixed-signal simulation
- Strong debugging skills across analog and digital domains
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968