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Locum Asic Rtl Design Engineer Jobs in California

Jobsbridge

ASIC Engineer

San Jose, CA

$194K/yr

ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etched

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Mercor

RTL Design Engineer - AI Tools

San Francisco, CA · Remote

$100 - $175/hr

Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · Hybrid

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · Hybrid

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · On-site

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...

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Locum Asic Rtl Design Engineer information

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

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Locum Asic Rtl Design Engineer jobs near you
Principal FPGA / RTL Design Engineer - Signal Processing

Principal FPGA / RTL Design Engineer - Signal Processing

Silvus Technologies

Irvine, CA • On-site

$132K - $181K/yr

Other

Posted 26 days ago

Job description

THE OPPORTUNITY

Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who will report to the Senior Engineering Director in Irvine and work closely with the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects aimed at addressing challenging real-world communication needs. 

This Principal FPGA / RTL Design Engineer is 100% onsite, Monday through Friday, at Silvus Technologies' Engineering and R&D Office in Irvine, CA, near the vibrant Irvine Spectrum.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion.

ROLE AND RESPONSIBILITIES

  • Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks.
  • RTL coding, simulation, and test bench development.
  • FPGA synthesis and timing closure.
  • Hardware verification and troubleshooting; familiarity with logic analyzers.
  • Provide support to the RF and Software Engineering teams.

REQUIRED QUALIFICATIONS

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields.
  • Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or related fields.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing (DSP) designs.
  • Deep knowledge of RTL design fundamentals using Verilog and System-Verilog.
  • Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
  • Must be a U.S. Citizen due to clients under U.S. government contracts.
  • All employment is contingent upon the successful clearance of a background check and drug testing..

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

  • MS. or Ph.D. degree in Electrical Engineering, Computer Science, or relevant fields.
  • Basic MATLAB skills.
  • Solid knowledge and understanding of scripting languages such as Perl and Python.
  • Strong communication and presentation skills.
  • Experience with wireless communication systems on FPGA or ASIC designs.

WORKING CONDITIONS & PHYSICAL REQUIREMENTS

  • Office environment.
  • Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.
  • While performing the duties of this job, the employee is required to do the following:
    • Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.
    • Perform bending and reaching movements to place items on lower and higher shelves.
    • Kneeling or squatting to access lower shelves.
    • Walking/Moving in the labs

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