Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
RTL Design Engineer (Silicon Engineering)
$145K - $195K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
RTL Design Engineer (Silicon Engineering)
$145K - $195K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
Quick apply
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Principal FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
Principal FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
ASIC Engineer
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
ASIC Engineer
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Locum Asic Rtl Design Engineer information
What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in California? The most popular types of Asic Rtl Design Engineer jobs in California are:
What are popular job titles related to Locum Asic Rtl Design Engineer jobs in California? For Locum Asic Rtl Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Locum Asic Rtl Design Engineer jobs in California look for? The top searched job categories for Locum Asic Rtl Design Engineer jobs in California are:
What cities in California are hiring for Locum Asic Rtl Design Engineer jobs? Cities in California with the most Locum Asic Rtl Design Engineer job openings:
Full-time
Posted 7 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure subsystems that protect the entire Apple SoC. In this role, you will design the state-of-the-art hardware defenses that prevent complex side channel attacks and ensure the integrity of our customers' most sensitive data across Apple's product line. Our work spans cryptographic engines, side channel attack monitors, data protection logics etc that make Apple devices the most secure consumer electronics in the world.
Description
As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will include:
• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met.
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.
Minimum Qualifications
BS in Electrical Engineering, Computer Engineering or a relevant field and 3 years of industry experience
3 years of RTL design experience using Verilog or SystemVerilog.
Preferred Qualifications
Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and verification.
Familiarity with low-power design techniques and UPF (Unified Power Format).
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
Background in cryptography and cryptographic algorithm implementation.
Experience with hardware security concepts including key management, physical attack and countermeasures.
Experience with clock and reset architecture at the subsystem level
Strong knowledge of AMBA bus protocols (AXI, AHB, APB).
Experience with hardware security concepts including key management, physical attack and countermeasures
Description
As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will include:
• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met.
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.
Minimum Qualifications
BS in Electrical Engineering, Computer Engineering or a relevant field and 3 years of industry experience
3 years of RTL design experience using Verilog or SystemVerilog.
Preferred Qualifications
Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and verification.
Familiarity with low-power design techniques and UPF (Unified Power Format).
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
Background in cryptography and cryptographic algorithm implementation.
Experience with hardware security concepts including key management, physical attack and countermeasures.
Experience with clock and reset architecture at the subsystem level
Strong knowledge of AMBA bus protocols (AXI, AHB, APB).
Experience with hardware security concepts including key management, physical attack and countermeasures
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976