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Layout Design Engineer Jobs in California (NOW HIRING)

Pacer Group

Memory Layout Engineer

Irvine, CA · On-site

Memory Layout Engineer Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ ... Design and implement custom memory layouts for advanced technology nodes, collaborating with ...

Nvidia

Senior Mask Design Engineer

Santa Clara, CA · Hybrid

$122K - $164K/yr

Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...

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Layout Design Engineer information

See California salary details

$44.4K

$119.3K

$183.1K

How much do layout design engineer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for layout design engineer in California is $119,266.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,800.00 and $142,100.00 per year, depending on experience, location, and employer.

What is a Layout Design Engineer job?

A Layout Design Engineer is responsible for designing and optimizing the physical layout of integrated circuits (ICs) in semiconductor chips. They work closely with circuit designers to ensure that the layout meets performance, power, and area constraints while adhering to manufacturing and design rules. Their role involves using EDA tools for placement, routing, and verification of chip layouts. They also conduct design rule checks (DRC) and layout versus schematic (LVS) verification to ensure design accuracy.

What are the key skills and qualifications needed to thrive in the Layout Design Engineer position, and why are they important?

To thrive as a Layout Design Engineer, you need strong skills in electronic circuit design, physical layout principles, and a background in electrical or electronics engineering, typically supported by a relevant bachelor's degree. Proficiency with EDA tools such as Cadence, Mentor Graphics, or Synopsys, and knowledge of industry standards (e.g., IPC) are essential. Exceptional attention to detail, problem-solving, and effective teamwork and communication skills help set candidates apart. These capabilities ensure precise, manufacturable layouts and smooth collaboration with multidisciplinary teams to meet project goals and deadlines.

What does a typical day look like for a Layout Design Engineer?

A typical day for a Layout Design Engineer involves translating schematic designs into detailed physical layouts using specialized CAD tools, collaborating closely with circuit designers to optimize for performance and manufacturability. You may spend time reviewing design rule checks (DRC), participating in team meetings to discuss project progress or resolve technical challenges, and coordinating with fabrication or test engineers to ensure successful implementation. The role requires both independent focus and frequent teamwork, offering a dynamic mix of technical and collaborative tasks. Depending on the company, you might also be involved in process improvement initiatives or mentoring junior engineers as you gain experience.

What are popular job titles related to Layout Design Engineer jobs in California? For Layout Design Engineer jobs in California, the most frequently searched job titles are:
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What cities in California are hiring for Layout Design Engineer jobs? Cities in California with the most Layout Design Engineer job openings:
Layout Design Engineer jobs near you
Infographic showing various Layout Design Engineer job openings in California as of June 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $119,266 per year, or $57.3 per hour.
Memory Layout Engineer

Memory Layout Engineer

Pacer Group

Irvine, CA • On-site

Contractor

Posted 27 days ago

Job description

Job Title: Memory Layout Engineer
Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ)
Job Duration: 3 Months, Contract to Hire
 
Job Responsibilities: 
  • Design and implement custom memory layouts for advanced technology nodes, collaborating with circuit designers to optimize performance, power, and area.
  • Mitigate layout design effects such as N-well proximity effect, diffusion spacing effect, and length of diffusion effects.
  • Collaborate with SoC partners to develop cutting-edge SRAM and Register File layout designs.
  • Participate in design reviews, to improve the quality of memory layouts.
  • Stay up to date with the latest industry trends and developments in memory layout design.
  • Perform physical verification (LVS, DRC, ANT, etc.) and debug memory layout.
  • Leading and mentoring junior layout engineers and providing guidance on layout techniques.
  • The ability to adhere to project timelines to ensure deliveries are met according to project schedules.
  • Effectively communicate with the design team to clarify and realize the layout requirements based on the schematic design intent.
  • Must be able to effectively switch between manufacturing nodes with minimal ramp.
Qualifications:
  •  7+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advanced nodes including FinFET technologies
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Excellent programming skills in languages: SKILL, Perl; Python is a plus
  • Strong fundamentals in software development
  • Solid experience with EMIR (RV), Physical design verification (DRC/LVS/PEX/ERC), waiver
  • Working knowledge of circuit design concepts such as device characteristics, SPICE and Verilog netlists and simulation
  • Excellent communication and interpersonal skills
Mandatory Skills:
  • Synopsys/Cadence Analog Layout Tools (Preference: 5)
  • Memory design and layout (Preference: 5)
  • Python (Preference: 2)?