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Junior Rtl Design Engineer Jobs in Seattle, WA (NOW HIRING)

Mundi

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190 - $280/hr

Engineered to survive the harshest radiation environments and to fully capitalize on today's and ... You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ...

Socket.dev

ASIC Design Verification Engineer

Seattle, WA · On-site

$130 - $200/hr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

New

Microsoft

Senior Silicon Design Engineer

Redmond, WA · On-site

$119K - $234K/yr

... Level (RTL) design, synthesis/Lint/CDC/FEV and System on Chip (SOC) integration on different ... Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND ...

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon ... and design engineers to implement digital logic functions in FPGAs Collaborate with system ...

Nvidia

Senior Digital Design Engineer

Redmond, WA · On-site

We are looking for a Senior Digital Design Engineer to join our Semi-Custom Silicon products group ... Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified ...

Ashby

Design Engineer - Americas

Seattle, WA · Remote

$126K - $250K/yr

Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...

K2 Space

Senior ASIC Emulation Engineer

Seattle, WA

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity ...

System One

Junior I & C Design Engineer

Bellevue, WA · On-site

I&C Design Engineer Location: Bellevue, WA Job Type: Contract Schedule: 40 hours/week System One is seeking an experienced Instrumentation & Controls (I&C) Design Engineer to support the design and ...

System One

Junior I & C Design Engineer

Bellevue, WA · On-site

I&C Design Engineer Location: Bellevue, WA Job Type: Contract Schedule: 40 hours/week System One is seeking an experienced Instrumentation & Controls (I&C) Design Engineer to support the design and ...

System One

Junior I & C Design Engineer

Bellevue, WA · On-site

I&C Design Engineer Location: Bellevue, WA Job Type: Contract Schedule: 40 hours/week System One is seeking an experienced Instrumentation & Controls (I&C) Design Engineer to support the design and ...

System One

Junior I & C Design Engineer

Bellevue, WA · On-site

I&C Design Engineer Location: Bellevue, WA Job Type: Contract Schedule: 40 hours/week System One is seeking an experienced Instrumentation & Controls (I&C) Design Engineer to support the design and ...

System One

Junior I & C Design Engineer

Bellevue, WA · On-site

I&C Design Engineer Location: Bellevue, WA Job Type: Contract Schedule: 40 hours/week System One is seeking an experienced Instrumentation & Controls (I&C) Design Engineer to support the design and ...

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Showing results 21-40

All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Seattle, WA

Junior Rtl Design Engineer information

See Seattle, WA salary details

$38.1K

$81.7K

$124.6K

How much do junior rtl design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for junior rtl design engineer in Seattle, WA is $81,710.00, according to ZipRecruiter salary data. Most workers in this role earn between $55,200.00 and $91,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are popular job titles related to Junior Rtl Design Engineer jobs in Seattle, WA? For Junior Rtl Design Engineer jobs in Seattle, WA, the most frequently searched job titles are:
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Junior Rtl Design Engineer jobs near you

FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX

Redmond, WA • On-site

$145K - $195K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 19 days ago

SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

15th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog
  • Optimize designs for power, performance and area
  • Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
  • Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
  • Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
  • Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL

PREFERRED SKILLS AND EXPERIENCE:
  • ASIC/FPGA system integration experience
  • Proficiency in Python, C/C++, and Bash
  • Experience in designing DSP, digital communication system datapath blocks, and/or modem design
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass), FPGA tools (e.g. Xilinx Vivado, Altera Quartus II)
  • Experience and understanding of AXI/AHB/APB protocols
  • Strong foundation in electrical engineering fundamentals
  • Experience debugging complex PCBs containing Microprocessors and FPGAs in the lab using equipment such as oscilloscopes and spectrum analyzers
  • Ability to work in a dynamic environment with changing needs and requirements
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Demonstrated ability to work in a highly cross-functional role
  • Enjoys being challenged and learning new skills
  • Master's in Electrical/Computer Engineering or related field

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:
Pay range:
ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year
ASIC Design Engineer/Level II: $145,000.00 - $195,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
    Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to

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About SpaceX

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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