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Junior Rtl Design Engineer Jobs in Washington (NOW HIRING)

Next Step Systems

DSP/FEC Engineer

Linthicum, MD · On-site

$141K - $164K/yr

DSP/FEC Engineer, Linthicum Heights, MD We are looking for multiple DSP/FEC Engineer candidates at ... Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description ...

Next Step Systems

DSP Communications Engineer

Linthicum, MD · On-site

$141K - $164K/yr

Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...

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All JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Washington

Junior Rtl Design Engineer information

See Washington salary details

$37.9K

$81.3K

$124K

How much do junior rtl design engineer jobs pay per year?

As of Jun 21, 2026, the average yearly pay for junior rtl design engineer in Washington is $81,320.00, according to ZipRecruiter salary data. Most workers in this role earn between $54,900.00 and $90,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are popular job titles related to Junior Rtl Design Engineer jobs in Washington? For Junior Rtl Design Engineer jobs in Washington, the most frequently searched job titles are:
What job categories do people searching Junior Rtl Design Engineer jobs in Washington look for? The top searched job categories for Junior Rtl Design Engineer jobs in Washington are:
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Junior Rtl Design Engineer jobs near you
Senior ASIC Physical Design Engineer

Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory

Laurel, MD • On-site

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 5 days ago

Johns Hopkins Applied Physics Laboratory rating

9.9

Company rating: 9.9 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

1st of 57 rated research

Job description

Description
Do you love building and prototyping robust electrical systems?
Are you passionate about providing real impact to the country's toughest national security problems?
If so, we're looking for someone like you to join our team at APL.
The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives.
We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC.
As a Senior ASIC Physical Design Engineer...
  • Your primary responsibility will be digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
  • You will contribute to process selection for new designs and proposals
  • You will floorplan the top-level layout of the digital and mixed-signal ASICs
  • You will perform timing analysis and design partitioning
  • You will perform SCAN and BIST insertion for maximum defect coverage
  • You will work with digital designers to debug and address back-end related RTL and gate-level issues
  • You will perform all physical verification, including DRC, DRC+, MCD, and LVS
  • You will perform custom physical layout
  • You may assist with ASIC design environment enhancements and scripting
  • You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
  • You will build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
  • You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
  • You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
  • You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution

Qualifications
You meet our minimum qualifications for the job if you...
  • Possess an Associate's degree in a technical field, or a combination of equivalent level experience/education/certifications.
  • Are skilled at using Cadence ASIC design tools for back-end flow implementation
  • Are skilled at using Siemens Calibre physical verification tools
  • Have 6+ years of experience specifically performing back-end ASIC design
  • Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.

You'll go above and beyond our minimum requirements if you...
  • Have experience with custom physical layout in Cadence Virtuoso
  • Are skilled at using Siemens ASIC design tools for back-end flow implementation
  • Have extensive knowledge and experience in ASIC technology characterization for process selection
  • Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.

About Us
Why Work at APL?
The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates.
At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers.
All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact Accessibility@jhuapl.edu.
The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis.
Minimum Rate
$105,000 Annually
Maximum Rate
$290,000 Annually

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