We need an RTL designer who understands that correctness has to be established through rigorous ... What You'll Do - Own RTL design tasks -- Develop RTL with a focus on correctness: bus fabric ...
We need an RTL designer who understands that correctness has to be established through rigorous ... What You'll Do - Own RTL design tasks -- Develop RTL with a focus on correctness: bus fabric ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
We need an RTL designer who understands that correctness has to be established through rigorous ... What You'll Do - Own RTL design tasks - Develop RTL with a focus on correctness: bus fabric ...
Senior ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$142K - $150K/yr
We need an RTL designer who understands that correctness has to be established through rigorous ... What You'll Do - Own RTL design tasks - Develop RTL with a focus on correctness: bus fabric ...
Lead ASIC Digital Design Engineer
$176K - $187K/yr
We need an RTL designer at heart -- someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions. The right candidate is a self-starter ...
Lead ASIC Digital Design Engineer
$176K - $187K/yr
We need an RTL designer at heart -- someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions. The right candidate is a self-starter ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$176K - $187K/yr
We need an RTL designer at heart - someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions. The right candidate is a self-starter who ...
Lead ASIC Digital Design Engineer
Annapolis Junction, MD · On-site +1
$176K - $187K/yr
We need an RTL designer at heart - someone who thinks in architecture and microarchitecture, and understands the downstream implications of design decisions. The right candidate is a self-starter who ...
Programmable Logic Design Engineer - Temporary
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders * Proven track record to design and implement ...
Programmable Logic Design Engineer - Temporary
$193K - $290K/yr
Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders * Proven track record to design and implement ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
DSP Communications Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various ...
DSP/FEC Engineer
Linthicum, MD · On-site
$141K - $164K/yr
Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various ...
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
Minimum Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various engineering ...
Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various ...
Preferred Qualifications: - Familiarity with FPGA and RTL design including hardware description languages (Verilog, System Verilog, VHDL). - Good knowledge and understanding across various ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Electrical Engineer
Linthicum, MD · On-site
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Minimum Qualifications: - 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.). - 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. - 3+ years of ...
Senior FPGA Electrical Engineer
Linthicum, MD · On-site
$102K - $138K/yr
Minimum Qualifications: - 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.). - 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. - 3+ years of ...
Own RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. * Work closely with DSP, software, hardware, and systems engineers to turn algorithm ...
New
Own RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. * Work closely with DSP, software, hardware, and systems engineers to turn algorithm ...
New
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system integration, and thrives in a collaborative, multi-disciplinary environment delivering mission-critical ...
Quick apply
Senior FPGA Engineer
Fairfax, VA · On-site
$97K - $181K/yr
The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system integration, and thrives in a collaborative, multi-disciplinary environment delivering mission-critical ...
FPGA/ASIC Design Engineer (Secret) - Reston, VA - 5137
Reston, VA · On-site
$128K - $176K/yr
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate test plans * Perform module level verification, synthesis/STA, Lab debug, SW driven validation on ...
FPGA/ASIC Design Engineer (Secret) - Reston, VA - 5137
Reston, VA · On-site
$128K - $176K/yr
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate test plans * Perform module level verification, synthesis/STA, Lab debug, SW driven validation on ...
Key Responsibilities • Design, develop, integrate, and test advanced digital and mixed-signal electronic systems. • Develop FPGA firmware using Xilinx SoC platforms, VHDL, RTL, and embedded ...
Key Responsibilities • Design, develop, integrate, and test advanced digital and mixed-signal electronic systems. • Develop FPGA firmware using Xilinx SoC platforms, VHDL, RTL, and embedded ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
... design within ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer ...
FPGA/ASIC Design Engineer with Security Clearance
Herndon, VA · On-site
$115/hr
Derive FPGA design specifications from system requirements Develop detailed FPGA architecture for implementation Implement design in RTL (VHDL) and perform module level simulations Perform Synthesis ...
FPGA/ASIC Design Engineer with Security Clearance
Herndon, VA · On-site
$115/hr
Derive FPGA design specifications from system requirements Develop detailed FPGA architecture for implementation Implement design in RTL (VHDL) and perform module level simulations Perform Synthesis ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Minimum Qualifications: - 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.). - 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. - 3+ years of ...
Senior FPGA Engineer
Linthicum, MD · On-site
$128K - $164K/yr
Minimum Qualifications: - 8+ years of experience designing/testing with FPGAs (Xilinx, Altera, etc.). - 8+ years of experience with SystemVerilog, Verilog, or VHDL RTL design. - 3+ years of ...
Engineer
Fairfax, VA · On-site
Bachelor's degree from an accredited university in STEM field OR a combination of education and relevant experience. * 5+ years of RTL design for FPGAs in VHDL or Verilog, or System Verilog ...
Engineer
Fairfax, VA · On-site
Bachelor's degree from an accredited university in STEM field OR a combination of education and relevant experience. * 5+ years of RTL design for FPGAs in VHDL or Verilog, or System Verilog ...
Engineer
Fairfax, VA · On-site
Bachelor's degree from an accredited university in STEM field OR a combination of education and relevant experience. * 5+ years of RTL design for FPGAs in VHDL or Verilog, or System Verilog ...
Engineer
Fairfax, VA · On-site
Bachelor's degree from an accredited university in STEM field OR a combination of education and relevant experience. * 5+ years of RTL design for FPGAs in VHDL or Verilog, or System Verilog ...
Rtl Design information
What are the key skills and qualifications needed for RTL design?
To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.
What does an RTL design engineer do?
A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.
What is an RTL design?
An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.
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What are popular job titles related to Rtl Design jobs in Washington? For Rtl Design jobs in Washington, the most frequently searched job titles are:
What job categories do people searching Rtl Design jobs in Washington look for? The top searched job categories for Rtl Design jobs in Washington are:
What cities in Washington are hiring for Rtl Design jobs? Cities in Washington with the most Rtl Design job openings:
Senior ASIC Digital Design Engineer
Annapolis Junction, MD • On-site
Full-time
Re-posted 24 days ago
General Dynamics Mission Systems rating
7.9
Based on 30 frontline employees who took The Breakroom Quiz
127th of 242 rated software companies
Job description
Education Requirements:
Requires a Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree plus 3 years of job-related experience.
Clearance Requirements:
Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
We're looking for an Advanced ASIC Design Engineer with solid hands-on experience in RTL design and a foundational understanding of the full ASIC/FPGA design lifecycle. This is a technical role for someone who is ready to take on meaningful ownership of design tasks within a collaborative, high-performing team.
If your career has been primarily running P&R tools, this probably isn't the right fit. We also need someone who has moved beyond the "burn it and see if it works" model of FPGA development — on ASIC, you don't get that luxury. We need an RTL designer who understands that correctness has to be established through rigorous simulation, formal verification, and independent review long before anything gets near silicon.
The right candidate has worked in larger, structured design environments where verification is a discipline in its own right — with dedicated verification partners, formal review processes, and clear functional closure criteria. A self-starter who can work independently on assigned tasks, drives progress without constant direction, and brings a problem-solving mindset to everything they touch.
What You'll Do
- Own RTL design tasks — Develop RTL with a focus on correctness: bus fabric integrity, clock domain crossings, reset order-of-operations, and design-for-verification
- Contribute to timing closure — Work through synthesis, place and route, and static timing analysis; identify root causes of timing failures and contribute to fixes
- Support verification efforts — Execute test and simulation plans in coordination with a dedicated verification team; understand and work within a formal verification process; verify results and help drive closure on failures
- Participate in JIRA triage — Review incoming issues and help maintain an accurate and actionable backlog
- Participate in code reviews — Engage in RTL code reviews, providing and receiving constructive technical feedback
- Support program planning — Provide input on task status, schedule risk, and level of effort to support IMS and EV reporting
- Support proposals — Contribute to basis of estimates (BOEs) for proposals, providing technical input on scope and level of effort for assigned design tasks
- Support technology evaluation — Assist in assessing foundry technologies, device libraries, IP cores, and EDA tooling
- Collaborate broadly — Participate in Integrated Product Teams and working groups
What We're Looking For
- 5–8+ years of ASIC/FPGA design experience, with meaningful time spent as an RTL designer
- Experience working in larger, structured design teams with formal verification processes and independent verification partners — not solely in small-team or solo development environments
- Demonstrated understanding that design correctness is established through simulation, formal verification, and peer review — not through iteration on hardware
- Some experience contributing to ASIC tape-out efforts is a plus
- Familiarity with FinFET process nodes (7nm, 5nm, or similar) is a differentiator
- Familiarity with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
- Working knowledge of:
- RTL design and microarchitecture
- Bus fabric design and verification
- Clock domain crossing (CDC) analysis
- Reset sequencing and validation
- Timing closure fundamentals
- Power analysis basics
Skills & Knowledge
- Solid understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
- Familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
- Ability to work independently on assigned tasks while coordinating effectively within the team
- Familiarity with vendor and foundry capabilities
- Proficiency in JIRA for issue tracking and backlog management
- Proficiency in Microsoft Office for documentation and communication
Why This Role
You won't be handed a spec and told to code. You'll take real ownership of design tasks, with exposure across the full ASIC lifecycle and the opportunity to grow alongside experienced engineers. This is a role where your work matters, your initiative is recognized, and the team values engineers who take ownership and see problems through to resolution.
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
USD $142,166.00 - USD $150,000.00 /Yr.
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans
What General Dynamics Mission Systems employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About General Dynamics Mission Systems
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
10,000+ Employees
Headquarters location
Fairfax, VA, US
Year founded
1952