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Junior Ic Layout Jobs (NOW HIRING)

Jr. ASIC Design Engineer

Batavia, NY ยท Hybrid

$70K - $93K/yr

Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...

Jr. ASIC Design Engineer

Batavia, IL ยท On-site

$70K - $93K/yr

Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...

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Junior Ic Layout information

See salary details

$33.5K

$71.8K

$109.5K

How much do junior ic layout jobs pay per year?

As of Jun 16, 2026, the average yearly pay for junior ic layout in the United States is $71,799.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,500.00 and $80,000.00 per year, depending on experience, location, and employer.

What are some typical challenges junior IC layout engineers face when transitioning from academic projects to professional environments?

Junior IC layout engineers often find that transitioning from academic assignments to industry projects involves adapting to stricter design rules, tighter deadlines, and more complex verification processes. In professional environments, they must collaborate closely with circuit designers and verification engineers, ensuring that layouts meet both functional and manufacturability requirements. Additionally, learning to use advanced EDA tools efficiently and understanding company-specific workflow standards are common hurdles. Support from senior team members and proactive communication can help overcome these challenges and accelerate skill development.

What are the key skills and qualifications needed to thrive as a Junior IC Layout Engineer, and why are they important?

To thrive as a Junior IC Layout Engineer, you need a solid understanding of semiconductor physics, circuit design basics, and relevant engineering degrees or coursework. Proficiency in CAD layout tools such as Cadence Virtuoso, as well as familiarity with design rule checks (DRC) and LVS tools, is typically required. Attention to detail, problem-solving skills, and effective communication are essential soft skills for collaborating with design teams and ensuring design accuracy. These competencies are vital for producing reliable, manufacturable integrated circuit layouts that meet performance and quality standards.

What are Junior IC Layout Engineers?

Junior IC (Integrated Circuit) Layout Engineers are entry-level professionals who assist in designing the physical layout of integrated circuits using specialized CAD tools. They work closely with senior engineers to convert circuit schematics into actual silicon layouts, ensuring that the designs meet performance, area, and power requirements. Their responsibilities typically include layout drawing, verification, and assisting in design rule checks under supervision. Junior IC Layout Engineers play a crucial role in the development of microchips used in electronics. This position is ideal for those with a background in electrical engineering or microelectronics and a keen attention to detail.

What is the difference between Junior Ic Layout vs Senior Ic Layout?

AspectJunior Ic LayoutSenior Ic Layout
ExperienceEntry-level, 0-2 yearsAdvanced, 3+ years
ResponsibilitiesAssisting in layout design, following guidelinesLeading layout projects, optimizing designs
SkillsBasic CAD tools, fundamental IC design knowledgeExpertise in CAD, design optimization, mentorship
CertificationsRelevant coursework or certificationsAdvanced certifications preferred

The main difference between Junior Ic Layout and Senior Ic Layout lies in experience, responsibilities, and skill level. Junior roles focus on assisting and learning, while senior roles involve leading projects and providing expertise. Both positions are essential in the IC design industry, with senior roles requiring more experience and advanced skills.

More about Junior Ic Layout jobs
What cities are hiring for Junior Ic Layout jobs? Cities with the most Junior Ic Layout job openings:
What are the most commonly searched types of Ic Layout jobs? The most popular types of Ic Layout jobs are:
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What job categories do people searching Junior Ic Layout jobs look for? The top searched job categories for Junior Ic Layout jobs are:
Infographic showing various Junior Ic Layout job openings in the United States as of June 2026, with employment types broken down into 92% Full Time, 6% Part Time, and 2% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $71,799 per year, or $34.5 per hour.
Principal Design Engineer

Principal Design Engineer

Navitas Semiconductor

Torrance, CA โ€ข On-site

Full-time

Medical, Dental, Vision, PTO

Posted 7 days ago


Job description

Job Purpose:
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC designย engineer to lead the architecture, design, and silicon execution of next-generation power management ICs.ย This role is hands-on and technical, with end-to-end ownership from concept through production, andย close collaboration with systems, device, layout, and validation teams. This is a key technical expertย position for engineers who have successfully brought power ICs into high-volume production and want toย shape future architectures.


Key Responsibilities and Duties:
โ€ข Lead the architecture, design, and verification of power management ICs from transistor-levelย blocks to full top-level integration.
โ€ข Define and evaluate system-level trade-offs for next-generation power supplies in collaborationย with applications and systems teams.
โ€ข Drive IC architecture decisions for products including AC-DC, DC-DC, ACF, LLC, QR, andย related power topologies.
โ€ข Interface closely with device, modeling, and EDA teams to optimize device selection, models,ย and simulation methodologies.
โ€ข Guide and review physical layout and floor planning, providing clear feedback to ensure optimalย performance, reliability, and manufacturability.
โ€ข Own tape-out execution, ensuring designs meet performance, schedule, and quality requirements.
โ€ข Lead silicon bring-up, lab validation, debugging, and correlation versus simulation.
โ€ข Support yield improvement, failure analysis, and release to production.
โ€ข Mentor junior designers and contribute to best practices across the design organization.

Knowledge, Skills, Abilities, and Other Characteristics (KSAOโ€™s)
โ€ข Proven experience as chip lead or technical owner on at least one successful silicon program.
โ€ข Demonstrated track record of delivering power ICs from concept to high-volume production,ย including:
ย  ย  ย o Architecture definition
ย  ย  ย o Circuit design
ย  ย  ย o Layout supervision
ย  ย  ย o Post-extraction verification
ย  ย  ย o Lab characterization and debug
ย  ย  ย o Yield and failure analysis support
โ€ข Strong experience in AC-DC and/or DC-DC power IC design.
โ€ข Deep expertise in analog and mixed-signal building blocks such as:
ย  ย  ย o Bandgap references
ย  ย  ย o LDOs
ย  ย  ย o Comparators
ย  ย  ย o Charge pumps
ย  ย  ย o Operational amplifiers
โ€ข Clear written and verbal communication skills.
โ€ข Self-motivated, collaborative, and comfortable working in a fast-paced, startup-like environment.


Required Qualifications
Basicย 

โ€ข Degree in Electrical Engineering, Material Science, Applied Physics or related Fields
โ€ข Strong understanding of semiconductor device physics, SOA, and power transistors used in high-frequency switching.
โ€ข Solid knowledge of silicon fabrication processes and their impact on device models and circuitย performance.


Preferred:ย 
โ€ข MSEE + 7+ years or PhD + 5+ years of industry experience in analog or mixed-signal IC design.
โ€ข Proficiency with EDA tools, including:
ย  ย  ย o Cadence Virtuoso / Spectre
ย  ย  ย o Post-parasitic extraction simulation
ย  ย  ย o Monte Carlo and corner analysis
โ€ข Experience with DFT methodologies, characterization strategies, and production test planning.
โ€ข Hands-on lab experience with silicon validation, debug, and characterization.


What We Give:
โ€ข A high visibility opportunity to work on leading edge technology development with a mission to make the world better with advancing the technology that powers the future.
โ€ข Fast decision making and freedom to work on interesting problems that the world cares about.
โ€ข A mission to succeed with full support from management.
โ€ข Health, dental, and vision benefits, unlimited PTOย 
โ€ข Total Compensation includes base + bonus and stock awards, depending on experience