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Junior Ic Layout Jobs (NOW HIRING)

Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...

$157 - $227/hr

The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...

New

Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...

Showing results 41-60

Junior Ic Layout information

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$33.5K

$71.8K

$109.5K

How much do junior ic layout jobs pay per year?

As of Sep 7, 2026, the average yearly pay for junior ic layout in the United States is $71,799.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,500.00 and $80,000.00 per year, depending on experience, location, and employer.

What is a junior IC layout?

Junior IC (Integrated Circuit) Layout Engineers are entry-level professionals who assist in designing the physical layout of integrated circuits using specialized CAD tools. They work closely with senior engineers to convert circuit schematics into actual silicon layouts, ensuring that the designs meet performance, area, and power requirements. Their responsibilities typically include layout drawing, verification, and assisting in design rule checks under supervision. Junior IC Layout Engineers play a crucial role in the development of microchips used in electronics. This position is ideal for those with a background in electrical engineering or microelectronics and a keen attention to detail.

What are the key skills and qualifications needed to thrive as a junior IC layout engineer?

To thrive as a Junior IC Layout Engineer, you need a solid understanding of semiconductor physics, circuit design basics, and relevant engineering degrees or coursework. Proficiency in CAD layout tools such as Cadence Virtuoso, as well as familiarity with design rule checks (DRC) and LVS tools, is typically required. Attention to detail, problem-solving skills, and effective communication are essential soft skills for collaborating with design teams and ensuring design accuracy. These competencies are vital for producing reliable, manufacturable integrated circuit layouts that meet performance and quality standards.

What are some typical challenges junior IC layout engineers face when transitioning from academic projects to professional environments?

Junior IC layout engineers often find that transitioning from academic assignments to industry projects involves adapting to stricter design rules, tighter deadlines, and more complex verification processes. In professional environments, they must collaborate closely with circuit designers and verification engineers, ensuring that layouts meet both functional and manufacturability requirements. Additionally, learning to use advanced EDA tools efficiently and understanding company-specific workflow standards are common hurdles. Support from senior team members and proactive communication can help overcome these challenges and accelerate skill development.

What is the difference between Junior Ic Layout vs Senior Ic Layout?

AspectJunior Ic LayoutSenior Ic Layout
ExperienceEntry-level, 0-2 yearsAdvanced, 3+ years
ResponsibilitiesAssisting in layout design, following guidelinesLeading layout projects, optimizing designs
SkillsBasic CAD tools, fundamental IC design knowledgeExpertise in CAD, design optimization, mentorship
CertificationsRelevant coursework or certificationsAdvanced certifications preferred

The main difference between Junior Ic Layout and Senior Ic Layout lies in experience, responsibilities, and skill level. Junior roles focus on assisting and learning, while senior roles involve leading projects and providing expertise. Both positions are essential in the IC design industry, with senior roles requiring more experience and advanced skills.

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What cities are hiring for Junior Ic Layout jobs?

Cities with the most Junior Ic Layout job openings:

What are the most commonly searched types of Ic Layout jobs?

The most popular types of Ic Layout jobs are:

What states have the most Junior Ic Layout jobs?

States with the most job openings for Junior Ic Layout jobs include:

Infographic showing various Junior Ic Layout job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 83% Full Time, 11% Part Time, 2% Contract, and 3% Nights. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $71,799 per year, or $34.5 per hour.

Senior Staff Engineer, RFIC Design and AI Platforms

Murata America

San Diego, CA

Full-time

Posted 16 days ago


Job description

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.

Job Summary

This position is responsible for the development and deployment of intelligent automation systems for RF product development, including the application of agentic AI technologies. Working closely with software and AI development teams, you will identify high-value engineering use cases, define technical requirements, and develop tools and workflows that improve efficiency, quality, and time to market of RFIC product development.

This position is also responsible for the design and development of advanced RF Front End ICs for Front End Modules used in 5G and beyond flagship smartphones. The engineer will apply and validate AI-enabled design automation methodologies within active RFIC development programs. Products are expected to include multiple RF sub-circuits, including RF low noise amplifiers, switches, power amplifiers, tunable filters, passive RF components, and the analog and digital circuitry required to control them. Development areas may also include high-speed next generation optical analog and mixed-signal ICs for AI data centers. and infrastructure. This position directs the development of products throughout the entire product life cycle, from product definition through product release and end-of-life.

Senior Staff Engineers are expected to operate with significant autonomy, identify and frame complex technical challenges, define solution strategies, make sound technical tradeoff decisions, and influence the resources and cross-functional alignment required to complete major projects. In addition to their technical role, Senior Staff Engineers are expected to train and mentor more junior engineers and lead advanced developments that extend the technical capabilities of the organization.

A successful individual will have a thorough understanding of RF circuit design and the ability to direct and coordinate activities necessary to complete major projects requiring a wide variety of technical skills. The individual must have demonstrated experience in RF circuit analysis, design, test, product development, and mass production releases. As part of a cross-functional development team, the candidate will interact with other essential disciplines including Marketing, Process Technology Development, Device Modeling, Test Engineering, Software and AI Development, and Manufacturing.

Roles & Responsibilities

This position has responsibility for:

  • Serve as a technical authority for RFIC architecture, circuit design strategy, and product-level tradeoff decisions across performance, power, area, cost, manufacturability, yield, robustness, and schedule.
  • Provide technical mentoring to other design team members; partner with design management on resource planning, technical priorities, risk assessment, and cross-functional execution.
  • Lead the development, validation, and deployment of AI-enabled RFIC design automation methodologies that improve IC product development efficiency, quality, engineering insight, and time to market.
  • Identify, prioritize, and implement opportunities for EDA workflow orchestration, simulation execution and analysis, design-space exploration, verification, documentation, and product debug.
  • Partner with software and AI engineers to integrate these capabilities into scalable, validated, and reusable engineering workflows.
  • Develop ICs in RF SOI and other appropriate semiconductor technologies for RF frontend platform products.
  • Lead and provide technical direction in product design, including schematic capture, IC layout, simulation, package analysis, evaluation board development, test plan creation, validation, and product release.
  • Document relevant product, design, and methodology information to educate others on novel design techniques, enable reuse of engineering knowledge, and provide guidance on product usage. Support the development of structured engineering knowledge that can be leveraged by AI-enabled tools and workflows.
  • Lead cross-functional teams to achieve industry-leading product performance and meet development goals. Create, track, and report program technical milestones, identify technical risks, and drive resolution of critical design issues.
  • Identify opportunities where AI, automation, and advanced design methodologies can materially improve RFIC development. Evaluate emerging technologies, lead proof-of-concept activities, and drive establishment of methodologies that can be leveraged across multiple products and design teams.
  • Collaborate with Applications, Characterization, Product, Test, and Manufacturing Engineers to answer customer questions, assess field failures, support yield improvements, resolve production issues, and improve product performance and robustness.

Minimum Qualifications (Experience and Skills)

  • 9+ years of relevant RFIC design and product development experience, including demonstrated ownership of complex RFIC designs from concept through production release.
  • Expertise designing RFIC products in RF SOI, bulk CMOS, and/or BiCMOS technologies, with deep experience in one or more areas such as LNAs, RF switches, power amplifiers, RF frontend control circuitry, or other RF/analog building blocks.
  • Strong understanding of analog biasing and control circuitry.
  • Excellent RF design and analysis skillset, including knowledge of S-parameters, noise figure, stability, P1dB, harmonics, IMD, IIP2/IIP3, and the capability to design for and measure each parameter.
  • Strong understanding of CMOS devices and semiconductor technologies as they relate to circuit- and product-level performance tradeoffs.
  • Demonstrated ability to lead technical development and help develop the technical skills of other engineers.
  • Advanced working knowledge of analog and RF IC layout techniques and physical design considerations.
  • Strong programming or scripting capability for engineering automation, preferably including Python.
  • Experience developing or applying design-flow automation techniques to semiconductor or RF engineering workflows.
  • Familiarity with generative AI, large language models, agentic AI, or related AI-enabled engineering technologies.
  • Ability to evaluate AI-generated engineering results and establish appropriate validation and human-review methodologies.
  • Demonstrated ability to communicate and document design work, technical decisions, tradeoff analyses, and methodologies with clarity, completeness, and audience-appropriate detail.
  • Proficiency with RF IC EDA tools including Cadence Virtuoso, Keysight ADS, and EM simulators such as EMX and HFSS.

Education Requirements

  • MSEE or equivalent advanced technical education and relevant industry experience.

Work Environment

This job operates in a professional office environment. This role routinely uses standard office equipment.

 

Physical Demands

The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.

USD 208,851.58 - 271,522.09 per year


pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.
Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com