Principal Design Engineer
Torrance, CA ยท On-site
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC design ... layout, and validation teams. This is a key technical expert position for engineers who have ...
Torrance, CA ยท On-site
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC design ... layout, and validation teams. This is a key technical expert position for engineers who have ...
Torrance, CA ยท On-site
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC design ... layout, and validation teams. This is a key technical expert position for engineers who have ...
Batavia, NY ยท Hybrid
$70K - $93K/yr
Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...
Batavia, NY ยท Hybrid
$70K - $93K/yr
Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...
Batavia, IL ยท On-site
$70K - $93K/yr
Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...
Batavia, IL ยท On-site
$70K - $93K/yr
Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ... IC design. * Familiarity with principles of instrumentation for radiation detection with solid ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
San Francisco, CA ยท On-site
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
San Francisco, CA ยท On-site
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
Santa Clara, CA ยท On-site
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
Santa Clara, CA ยท On-site
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
... layout teams with strict best practices for parasitic mitigation and device matching. Mentor junior ... Expert-level proficiency with industry-standard IC design and verification toolchains (e.g ...
Santa Clara, CA ยท On-site
$159K - $164K/yr
This role involves working closely with design and layout teams to ensure the integrity and ... Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design ...
Santa Clara, CA ยท On-site
$159K - $164K/yr
This role involves working closely with design and layout teams to ensure the integrity and ... Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design ...
Santa Clara, CA ยท On-site
$159K - $164K/yr
This role involves working closely with design and layout teams to ensure the integrity and ... Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design ...
Santa Clara, CA ยท On-site
$159K - $164K/yr
This role involves working closely with design and layout teams to ensure the integrity and ... Develop and maintain advanced CAD and EDA tools and methodologies for digital and analog IC design ...
Cupertino, CA ยท On-site
$167K - $172K/yr
... Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs Schematic), PERC ... Develop and maintain verification runsets and methodologies - Mentor junior engineers on physical ...
Cupertino, CA ยท On-site
$167K - $172K/yr
... Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs Schematic), PERC ... Develop and maintain verification runsets and methodologies - Mentor junior engineers on physical ...
Cupertino, CA ยท On-site
$167K - $172K/yr
... Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs Schematic), PERC ... Develop and maintain verification runsets and methodologies - Mentor junior engineers on physical ...
Cupertino, CA ยท On-site
$167K - $172K/yr
... Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs Schematic), PERC ... Develop and maintain verification runsets and methodologies - Mentor junior engineers on physical ...
San Diego, CA ยท On-site
$213K - $298K/yr
Oversee layout, top-level integration, floorplanning, and verification of the overall design for ... and mentor junior engineers for best design practices in analog domain. Minimum Qualifications:
San Diego, CA ยท On-site
$213K - $298K/yr
Oversee layout, top-level integration, floorplanning, and verification of the overall design for ... and mentor junior engineers for best design practices in analog domain. Minimum Qualifications:
Bodega Bay, CA ยท On-site +1
$213K - $298K/yr
Oversee layout, top-level integration, floorplanning, and verification of the overall design for ... and mentor junior engineers for best design practices in analog domain. Minimum Qualifications:
Bodega Bay, CA ยท On-site +1
$213K - $298K/yr
Oversee layout, top-level integration, floorplanning, and verification of the overall design for ... and mentor junior engineers for best design practices in analog domain. Minimum Qualifications:
$33.5K - $40.4K
3% of jobs
$40.4K - $47.3K
20% of jobs
$48.8K is the 25th percentile. Wages below this are outliers.
$47.3K - $54.2K
7% of jobs
$54.2K - $61.1K
6% of jobs
$61.1K - $68K
12% of jobs
The median wage is $68.5K / yr.
$68K - $75K
17% of jobs
$78.6K is the 75th percentile. Wages above this are outliers.
$75K - $81.9K
17% of jobs
$81.9K - $88.8K
7% of jobs
$88.8K - $95.7K
4% of jobs
$95.7K - $102.6K
3% of jobs
$102.6K - $109.5K
2% of jobs
$33.5K
$71.8K
$109.5K
| Aspect | Junior Ic Layout | Senior Ic Layout |
|---|---|---|
| Experience | Entry-level, 0-2 years | Advanced, 3+ years |
| Responsibilities | Assisting in layout design, following guidelines | Leading layout projects, optimizing designs |
| Skills | Basic CAD tools, fundamental IC design knowledge | Expertise in CAD, design optimization, mentorship |
| Certifications | Relevant coursework or certifications | Advanced certifications preferred |
The main difference between Junior Ic Layout and Senior Ic Layout lies in experience, responsibilities, and skill level. Junior roles focus on assisting and learning, while senior roles involve leading projects and providing expertise. Both positions are essential in the IC design industry, with senior roles requiring more experience and advanced skills.

Full-time
Medical, Dental, Vision, PTO
Posted 7 days ago
Job Purpose:
Navitas Semiconductor is seeking a highly motivated and experienced analog / power IC designย engineer to lead the architecture, design, and silicon execution of next-generation power management ICs.ย This role is hands-on and technical, with end-to-end ownership from concept through production, andย close collaboration with systems, device, layout, and validation teams. This is a key technical expertย position for engineers who have successfully brought power ICs into high-volume production and want toย shape future architectures.
Key Responsibilities and Duties:
โข Lead the architecture, design, and verification of power management ICs from transistor-levelย blocks to full top-level integration.
โข Define and evaluate system-level trade-offs for next-generation power supplies in collaborationย with applications and systems teams.
โข Drive IC architecture decisions for products including AC-DC, DC-DC, ACF, LLC, QR, andย related power topologies.
โข Interface closely with device, modeling, and EDA teams to optimize device selection, models,ย and simulation methodologies.
โข Guide and review physical layout and floor planning, providing clear feedback to ensure optimalย performance, reliability, and manufacturability.
โข Own tape-out execution, ensuring designs meet performance, schedule, and quality requirements.
โข Lead silicon bring-up, lab validation, debugging, and correlation versus simulation.
โข Support yield improvement, failure analysis, and release to production.
โข Mentor junior designers and contribute to best practices across the design organization.
Knowledge, Skills, Abilities, and Other Characteristics (KSAOโs)
โข Proven experience as chip lead or technical owner on at least one successful silicon program.
โข Demonstrated track record of delivering power ICs from concept to high-volume production,ย including:
ย ย ย o Architecture definition
ย ย ย o Circuit design
ย ย ย o Layout supervision
ย ย ย o Post-extraction verification
ย ย ย o Lab characterization and debug
ย ย ย o Yield and failure analysis support
โข Strong experience in AC-DC and/or DC-DC power IC design.
โข Deep expertise in analog and mixed-signal building blocks such as:
ย ย ย o Bandgap references
ย ย ย o LDOs
ย ย ย o Comparators
ย ย ย o Charge pumps
ย ย ย o Operational amplifiers
โข Clear written and verbal communication skills.
โข Self-motivated, collaborative, and comfortable working in a fast-paced, startup-like environment.
Required Qualifications
Basicย
โข Degree in Electrical Engineering, Material Science, Applied Physics or related Fields
โข Strong understanding of semiconductor device physics, SOA, and power transistors used in high-frequency switching.
โข Solid knowledge of silicon fabrication processes and their impact on device models and circuitย performance.
Preferred:ย
โข MSEE + 7+ years or PhD + 5+ years of industry experience in analog or mixed-signal IC design.
โข Proficiency with EDA tools, including:
ย ย ย o Cadence Virtuoso / Spectre
ย ย ย o Post-parasitic extraction simulation
ย ย ย o Monte Carlo and corner analysis
โข Experience with DFT methodologies, characterization strategies, and production test planning.
โข Hands-on lab experience with silicon validation, debug, and characterization.
What We Give:
โข A high visibility opportunity to work on leading edge technology development with a mission to make the world better with advancing the technology that powers the future.
โข Fast decision making and freedom to work on interesting problems that the world cares about.
โข A mission to succeed with full support from management.
โข Health, dental, and vision benefits, unlimited PTOย
โข Total Compensation includes base + bonus and stock awards, depending on experience
Sourced by ZipRecruiter
Semiconductor and electronic component manufacturing
51 - 200 Employees
Torrance, CA, US
2013