... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
Senior Staff Engineer, RFIC Design and AI Platforms
San Diego, CA · On-site
$209 - $272/hr
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
Senior Staff Engineer, RFIC Design and AI Platforms
San Diego, CA · On-site
$209 - $272/hr
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
... junior engineers and lead advanced developments that extend the technical capabilities of the ... Lead and provide technical direction in product design, including schematic capture, IC layout ...
Full-Stack Web Developer Intern
Richardson, TX · On-site
$31 - $42/hr
Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...
Full-Stack Web Developer Intern
Richardson, TX · On-site
$31 - $42/hr
Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$157 - $227/hr
The role carries both hands‑on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
Full-Stack Web Developer Intern
Richardson, TX · On-site
$31 - $42/hr
Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...
Full-Stack Web Developer Intern
Richardson, TX · On-site
$31 - $42/hr
Current Junior or Senior in a Bachelor's degree program (graduating December 2028 or later) or a ... Familiarity with semiconductors or integrated circuit (IC) layout. This position is not eligible ...
Analog IC Design Engineer | Audio AAA
Dallas, TX · On-site
$183K/yr
Collaborate with systems, layout, and applications engineers to meet audio performance ... Mentor junior engineers on analog design fundamentals, simulation best practices, and design-for ...
Analog IC Design Engineer | Audio AAA
Dallas, TX · On-site
$183K/yr
Collaborate with systems, layout, and applications engineers to meet audio performance ... Mentor junior engineers on analog design fundamentals, simulation best practices, and design-for ...
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$220K/yr
The role carries both hands-on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
Principal IC Analog / Mixed Signal Design Engineer
Wilmington, MA · On-site
$220K/yr
The role carries both hands-on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
The role carries both hands-on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
The role carries both hands-on design ownership and technical leadership of junior and senior ... Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability ...
New
RF/Analog IC Design Engineer Santa Clara, California, United States of America RFIC Design
Santa Clara, CA · On-site
$168.60 - $252.80/hr
... generated layout. • Reviews block-level test plans and reviews test results and provides ... junior team members do the same. • Ensure that bugs are fully understood and analyzed ...
RF/Analog IC Design Engineer Santa Clara, California, United States of America RFIC Design
Santa Clara, CA · On-site
$168.60 - $252.80/hr
... generated layout. • Reviews block-level test plans and reviews test results and provides ... junior team members do the same. • Ensure that bugs are fully understood and analyzed ...
Sr. Principal Design Engineer CMOS
Manhattan Beach, CA · On-site
$142K - $213K/yr
Provide technical direction to layout and junior design engineers; ensure robust layout practices ... IC design experience for space, radiation-tolerant, or other harsh environments (rad-hard design ...
Sr. Principal Design Engineer CMOS
Manhattan Beach, CA · On-site
$142K - $213K/yr
Provide technical direction to layout and junior design engineers; ensure robust layout practices ... IC design experience for space, radiation-tolerant, or other harsh environments (rad-hard design ...
Principal PLL IC Design Engineer - TeraWave
Seattle, WA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Principal PLL IC Design Engineer - TeraWave
Seattle, WA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Principal PLL IC Design Engineer - TeraWave
San Francisco, CA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Principal PLL IC Design Engineer - TeraWave
San Francisco, CA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Lead/mentor junior engineers Qualifications: * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detailed oriented, with excellent problem-solving skills ...
Lead/mentor junior engineers Qualifications: * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detailed oriented, with excellent problem-solving skills ...
Principal PLL IC Design Engineer - TeraWave
Renton, WA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Principal PLL IC Design Engineer - TeraWave
Renton, WA · On-site
$269.17 - $376.84/hr
Overseeing layout, top-level integration, floorplanning, and verification of the overall design for ... Mentoring junior engineers for best design practices in analog domain.**Minimum Qualifications:
Senior Analog IC Design Engineer
San Jose, CA · On-site
$190 - $232/hr
Lead/mentor junior engineers Qualifications * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detail oriented, with excellent problem-solving skills ...
Senior Analog IC Design Engineer
San Jose, CA · On-site
$190 - $232/hr
Lead/mentor junior engineers Qualifications * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detail oriented, with excellent problem-solving skills ...
Lead/mentor junior engineers Qualifications: * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detailed oriented, with excellent problem-solving skills ...
Lead/mentor junior engineers Qualifications: * BS, MS, and/or PhD in Electrical Engineering or ... layout, and analog behavioral modeling * Detailed oriented, with excellent problem-solving skills ...
Junior Ic Layout information
See salary details
$33.5K - $40.4K
3% of jobs
$40.4K - $47.3K
20% of jobs
$48.8K is the 25th percentile. Wages below this are outliers.
$47.3K - $54.2K
7% of jobs
$54.2K - $61.1K
6% of jobs
$61.1K - $68K
12% of jobs
The median wage is $68.5K / yr.
$68K - $75K
17% of jobs
$78.6K is the 75th percentile. Wages above this are outliers.
$75K - $81.9K
17% of jobs
$81.9K - $88.8K
7% of jobs
$88.8K - $95.7K
4% of jobs
$95.7K - $102.6K
3% of jobs
$102.6K - $109.5K
2% of jobs
$33.5K
$71.8K
$109.5K
How much do junior ic layout jobs pay per year?
What is a junior IC layout?
What are the key skills and qualifications needed to thrive as a junior IC layout engineer?
What are some typical challenges junior IC layout engineers face when transitioning from academic projects to professional environments?
What is the difference between Junior Ic Layout vs Senior Ic Layout?
| Aspect | Junior Ic Layout | Senior Ic Layout |
|---|---|---|
| Experience | Entry-level, 0-2 years | Advanced, 3+ years |
| Responsibilities | Assisting in layout design, following guidelines | Leading layout projects, optimizing designs |
| Skills | Basic CAD tools, fundamental IC design knowledge | Expertise in CAD, design optimization, mentorship |
| Certifications | Relevant coursework or certifications | Advanced certifications preferred |
The main difference between Junior Ic Layout and Senior Ic Layout lies in experience, responsibilities, and skill level. Junior roles focus on assisting and learning, while senior roles involve leading projects and providing expertise. Both positions are essential in the IC design industry, with senior roles requiring more experience and advanced skills.
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Full-time
Posted 16 days ago
Job description
pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30-year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world-class capabilities with high-performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.
Job Summary
This position is responsible for the development and deployment of intelligent automation systems for RF product development, including the application of agentic AI technologies. Working closely with software and AI development teams, you will identify high-value engineering use cases, define technical requirements, and develop tools and workflows that improve efficiency, quality, and time to market of RFIC product development.
This position is also responsible for the design and development of advanced RF Front End ICs for Front End Modules used in 5G and beyond flagship smartphones. The engineer will apply and validate AI-enabled design automation methodologies within active RFIC development programs. Products are expected to include multiple RF sub-circuits, including RF low noise amplifiers, switches, power amplifiers, tunable filters, passive RF components, and the analog and digital circuitry required to control them. Development areas may also include high-speed next generation optical analog and mixed-signal ICs for AI data centers. and infrastructure. This position directs the development of products throughout the entire product life cycle, from product definition through product release and end-of-life.
Senior Staff Engineers are expected to operate with significant autonomy, identify and frame complex technical challenges, define solution strategies, make sound technical tradeoff decisions, and influence the resources and cross-functional alignment required to complete major projects. In addition to their technical role, Senior Staff Engineers are expected to train and mentor more junior engineers and lead advanced developments that extend the technical capabilities of the organization.
A successful individual will have a thorough understanding of RF circuit design and the ability to direct and coordinate activities necessary to complete major projects requiring a wide variety of technical skills. The individual must have demonstrated experience in RF circuit analysis, design, test, product development, and mass production releases. As part of a cross-functional development team, the candidate will interact with other essential disciplines including Marketing, Process Technology Development, Device Modeling, Test Engineering, Software and AI Development, and Manufacturing.
Roles & Responsibilities
This position has responsibility for:
- Serve as a technical authority for RFIC architecture, circuit design strategy, and product-level tradeoff decisions across performance, power, area, cost, manufacturability, yield, robustness, and schedule.
- Provide technical mentoring to other design team members; partner with design management on resource planning, technical priorities, risk assessment, and cross-functional execution.
- Lead the development, validation, and deployment of AI-enabled RFIC design automation methodologies that improve IC product development efficiency, quality, engineering insight, and time to market.
- Identify, prioritize, and implement opportunities for EDA workflow orchestration, simulation execution and analysis, design-space exploration, verification, documentation, and product debug.
- Partner with software and AI engineers to integrate these capabilities into scalable, validated, and reusable engineering workflows.
- Develop ICs in RF SOI and other appropriate semiconductor technologies for RF frontend platform products.
- Lead and provide technical direction in product design, including schematic capture, IC layout, simulation, package analysis, evaluation board development, test plan creation, validation, and product release.
- Document relevant product, design, and methodology information to educate others on novel design techniques, enable reuse of engineering knowledge, and provide guidance on product usage. Support the development of structured engineering knowledge that can be leveraged by AI-enabled tools and workflows.
- Lead cross-functional teams to achieve industry-leading product performance and meet development goals. Create, track, and report program technical milestones, identify technical risks, and drive resolution of critical design issues.
- Identify opportunities where AI, automation, and advanced design methodologies can materially improve RFIC development. Evaluate emerging technologies, lead proof-of-concept activities, and drive establishment of methodologies that can be leveraged across multiple products and design teams.
- Collaborate with Applications, Characterization, Product, Test, and Manufacturing Engineers to answer customer questions, assess field failures, support yield improvements, resolve production issues, and improve product performance and robustness.
Minimum Qualifications (Experience and Skills)
- 9+ years of relevant RFIC design and product development experience, including demonstrated ownership of complex RFIC designs from concept through production release.
- Expertise designing RFIC products in RF SOI, bulk CMOS, and/or BiCMOS technologies, with deep experience in one or more areas such as LNAs, RF switches, power amplifiers, RF frontend control circuitry, or other RF/analog building blocks.
- Strong understanding of analog biasing and control circuitry.
- Excellent RF design and analysis skillset, including knowledge of S-parameters, noise figure, stability, P1dB, harmonics, IMD, IIP2/IIP3, and the capability to design for and measure each parameter.
- Strong understanding of CMOS devices and semiconductor technologies as they relate to circuit- and product-level performance tradeoffs.
- Demonstrated ability to lead technical development and help develop the technical skills of other engineers.
- Advanced working knowledge of analog and RF IC layout techniques and physical design considerations.
- Strong programming or scripting capability for engineering automation, preferably including Python.
- Experience developing or applying design-flow automation techniques to semiconductor or RF engineering workflows.
- Familiarity with generative AI, large language models, agentic AI, or related AI-enabled engineering technologies.
- Ability to evaluate AI-generated engineering results and establish appropriate validation and human-review methodologies.
- Demonstrated ability to communicate and document design work, technical decisions, tradeoff analyses, and methodologies with clarity, completeness, and audience-appropriate detail.
- Proficiency with RF IC EDA tools including Cadence Virtuoso, Keysight ADS, and EM simulators such as EMX and HFSS.
Education Requirements
- MSEE or equivalent advanced technical education and relevant industry experience.
Work Environment
This job operates in a professional office environment. This role routinely uses standard office equipment.
Physical Demands
The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand; walk; use hands to finger, handle or feel; and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds.
USD 208,851.58 - 271,522.09 per year
pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver’s license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally-protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics.
Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: http://patents.psemi.com