Internship Defect Analyst Jobs (NOW HIRING)

Job Details:Job Description: 

At Intel's Logic Technology Development (LTD) we have continued to extend Moore's lawto beworld leaders in computing technology. To achieve the necessary scaling of our semiconductor manufacturing process, we have led the industry in developing enhancements such as strained silicon for carrier transport enhancement, high-k metal gates, and FINFETs.LTD has been at the center of every new development that has kept Moore's Law moving forward. Defect Metrology plays a key role in the development of every new siliconprocess development. Our analysis builds the plan that allows LTD to taketechnologyfrom the research phase to the high-volume manufacturing phase while maintaininghigh qualitystandards.IntheMIEorganization, we engineer world-class yields on D1 processes by driving defects down to Best-in-Class targets. As a Defect Metrology engineer, you willbe responsible foridentifyingall the defects that impact yield and performance inan advancedsilicon process technology. You will characterize the process usingcutting-edgemetrology tools. With this characterization, you willbe responsible forcreating the defectreductionroadmap. You will then work directly with modules and integration to drive that roadmap by developing and qualifying process fixes. This roleprovidesan opportunity to influence Intel's future process technologies that will keep Moore's Law moving forward.

Responsibilities/Duties include but not limited to:

• Provide navigation and leadership to meet Intel's yieldobjectivesutilizingstate of the artmetrology tools and QTMs.

• Organizing and presenting defect summaries to LTD engineering teams.

• Partnering with Intel Integration, Yield, and failure analysis labs to provide root cause for all defect issues.

• Instituterampto manufacturing volumes todemonstratethe technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology.

• Hold the team and collaborators accountable for quality through IMT and FTs.

• Work collaboratively as a part of the overall TD Defect metrology group.

• Role-model andestablishateamculture of trust, collaboration, safety, accountability, and excellence.

• Build strong relationships with other LTDprocessand design teams based on mutual trust and respect.

• An ideal candidate should be willing todemonstratethe below behavioral traits:

• Strong data analysis and problem debug skills.

• Excellent communication skills.

• Understand and adhere to key Intel values

Qualifications:

You mustpossessthe below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to theminimumrequirements and are considered a plus factor inidentifyingtop candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevantpreviousjob and internship experience.

Minimum Qualifications:

MustpossessaMaster'sdegree with 3+ years of experience, or PhD with 1+ years of experience in Computer Science, Physics, Material Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear engineering, Optics, or Chemistry (with focus on hands on experimental research)

Minimum of 1 year experience with one or more of the following:

• Materials characterization (SEM, TEM, etc.), materials fabrication, synthesis, metrology, statistical or data analysis (MATLAB, Excel, JMP, etc.)
• Semiconductor processing fundamentals (lithography, wetand ordry etch, chemical and or mechanical polishing, etc.), semiconductor and or transistor device physics, and design of experiments.

Preferred Qualifications:

Minimum of 1 year experience with one or more of the following:

• Demonstrate experience of Statistical Process Control SPC or Design of Experiments (DOE) principles.

• Expertise onsemiconductor physics.

• Expertise onsemiconductor processing.

• Expertise in Yield Improvement, Defect Improvement

• Brightfield, Darkfield, Voltage Contrast (VC)
• Experience with defect troubleshooting using programs similar or including Klarity, JMP, Model-Based Problem Solving (MBPS) or Fishbone Analysis

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Business group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $115,110.00-219,550.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.