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Ic Physical Design Engineer Jobs (NOW HIRING)

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Apply Early

Apple

IC Package Design Engineer

Austin, TX

$171K - $302K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Austin, TX

$171K - $302K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA

$120K - $210K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Austin, TX

$171K - $302K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

Physical Design Engineer

Bodega Bay, CA

$147K - $272K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$126K - $220K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Futran Tech Solutions Pvt. Ltd.

Physical Design Engineer

$139K - $143K/yr

Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...

Apple

Physical Design Engineer

Cupertino, CA

$181K - $318K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$126K - $220K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Apple

Physical Design Engineer

Bodega Bay, CA

$147K - $272K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

Apple

Physical Design Engineer

Cupertino, CA

$181K - $318K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Etched

Physical Design Engineer

Cupertino, CA · On-site

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Apple

Physical Design Engineer

Cupertino, CA

$126K - $220K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$126K - $220K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Google

Staff Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

... IC packaging. * Strong understanding of performance, power, and area trade-offs, alongside ... As a Staff Physical Design Engineer, you will lead the end-to-end physical design implementation of ...

Apple

Physical Design Engineer

Bodega Bay, CA

$147K - $272K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Etched

Physical Design Engineer

Cupertino, CA · On-site

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Wipro Limited

Physical Design Engineer

Austin, TX · On-site

$60K - $135K/yr

Physical Design Engineer City: Austin State/Province: Texas Posting Start Date: 6/18/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company ...

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Ic Physical Design Engineer information

See salary details

$95K

$141.5K

How much do ic physical design engineer jobs pay per year?

As of Jun 30, 2026, the average yearly pay for ic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is an IC Physical Design Engineer?

An IC Physical Design Engineer is a specialist who works on transforming a circuit design into a physical layout that can be fabricated on a silicon chip. They use electronic design automation (EDA) tools to handle tasks such as floorplanning, placement, routing, clock tree synthesis, and timing closure. Their work ensures that the integrated circuit meets performance, area, and power requirements while adhering to manufacturing constraints. IC Physical Design Engineers play a crucial role in the process of bringing semiconductor products from concept to production.

What are some common challenges faced by IC Physical Design Engineers during project tape-out?

IC Physical Design Engineers often encounter challenges such as meeting tight timing closure requirements, managing power and area constraints, and ensuring design rule compliance during tape-out. Collaborating effectively with cross-functional teams, such as verification and front-end design, is crucial to address last-minute changes or bug fixes. Additionally, handling large-scale data and optimizing tool flows for efficiency can be demanding but are essential for successful project delivery.

What is the difference between Ic Physical Design Engineer vs IC Verification Engineer?

AspectIC Physical Design EngineerIC Verification Engineer
Primary FocusPhysical layout, placement, routing, and timing optimization of integrated circuitsFunctional verification, testing, and validation of IC designs to ensure correctness
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages (HDL), testbench development, simulation tools
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, test environments, design verification platforms
Industry UsageSemiconductor companies, chip design firmsASIC/FPGA companies, semiconductor industry

While both roles are essential in IC development, the IC Physical Design Engineer focuses on the physical implementation of circuits, ensuring they fit and perform on silicon. In contrast, the IC Verification Engineer concentrates on testing and validating the design to catch errors before fabrication.

What are the key skills and qualifications needed to thrive as an IC Physical Design Engineer, and why are they important?

To excel as an IC Physical Design Engineer, you need a solid background in electrical engineering, VLSI design, and familiarity with semiconductor fabrication processes, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as experience with timing analysis, floorplanning, and physical verification, is typically required. Strong problem-solving skills, attention to detail, and effective teamwork are important soft skills that help you address design challenges and meet project deadlines. These skills and qualities are crucial for optimizing chip performance, ensuring manufacturability, and delivering successful silicon products.
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What cities are hiring for Ic Physical Design Engineer jobs? Cities with the most Ic Physical Design Engineer job openings:
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Ic Physical Design Engineer jobs near you
Infographic showing various Ic Physical Design Engineer job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 80% In-person, and 20% Hybrid job distribution, with an average salary of $139,408 per year, or $67 per hour.
Physical Design Engineer

Physical Design Engineer

iFlow Inc

Sunnyvale, CA • On-site

$159K - $164K/yr

Contractor

Posted 2 days ago

Be an early applicant

Key responsibilities

  • Define optimal floorplan, perform standard cell placement, optimization, and congestion analysis at block level.

  • Design, optimize, and verify clock networks, power grids, and perform timing closure using static timing analysis.

  • Manage chip-level floorplanning, integrate IP and sub-blocks, and perform final netlist-to-GDSII implementation with physical and electrical verification.

Job description


Job Title: Physical Design Engineer 
Location:Sunnyvale, CA OR Austin,TX
Duration: Long term
experience: 5–18 years only (No 18+ years profile)

Job Overview:
We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning.
Key Responsibilities:
Block-Level Physical Design:
• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure – Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure – Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.
Top-Level Physical Design:
• Chip-Level Floorplanning & Hierarchical Design – Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution – Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks – Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off – Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
• DFT Integration – Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.
 
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