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Ic Physical Design Engineer Jobs (NOW HIRING)

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

IC Package Design Engineer

Los Angeles, CA

$120K - $210K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Violet Ink

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Physical Design Engineer / Staff Engineer Location : San Jose CA Contract More than 12 months Relocation consultants are also considerable.. Job Responsibilities: We are seeking experienced Physical ...

Ambarella

$140K - $156K/yr

The Physical Design Engineer willbe an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edgelow powerAISoC ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Intel

Physical Design Engineer

Folsom, CA · On-site

$105K - $200K/yr

As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting-edge technology that ...

Intel

Physical Design Engineer

Austin, TX · On-site

$105K - $200K/yr

As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting-edge technology that ...

Apple

IC Package Design Engineer

Los Angeles, CA

$120K - $210K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

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All JobsIc Physical Design Engineer Jobs

Ic Physical Design Engineer information

See salary details

$95K

$141.5K

How much do ic physical design engineer jobs pay per year?

As of Jun 30, 2026, the average yearly pay for ic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is an IC Physical Design Engineer?

An IC Physical Design Engineer is a specialist who works on transforming a circuit design into a physical layout that can be fabricated on a silicon chip. They use electronic design automation (EDA) tools to handle tasks such as floorplanning, placement, routing, clock tree synthesis, and timing closure. Their work ensures that the integrated circuit meets performance, area, and power requirements while adhering to manufacturing constraints. IC Physical Design Engineers play a crucial role in the process of bringing semiconductor products from concept to production.

What are some common challenges faced by IC Physical Design Engineers during project tape-out?

IC Physical Design Engineers often encounter challenges such as meeting tight timing closure requirements, managing power and area constraints, and ensuring design rule compliance during tape-out. Collaborating effectively with cross-functional teams, such as verification and front-end design, is crucial to address last-minute changes or bug fixes. Additionally, handling large-scale data and optimizing tool flows for efficiency can be demanding but are essential for successful project delivery.

What is the difference between Ic Physical Design Engineer vs IC Verification Engineer?

AspectIC Physical Design EngineerIC Verification Engineer
Primary FocusPhysical layout, placement, routing, and timing optimization of integrated circuitsFunctional verification, testing, and validation of IC designs to ensure correctness
Skills & CertificationsVLSI design, EDA tools, CMOS fabrication knowledgeHardware description languages (HDL), testbench development, simulation tools
Work EnvironmentDesign teams, CAD tools, EDA softwareSimulation labs, test environments, design verification platforms
Industry UsageSemiconductor companies, chip design firmsASIC/FPGA companies, semiconductor industry

While both roles are essential in IC development, the IC Physical Design Engineer focuses on the physical implementation of circuits, ensuring they fit and perform on silicon. In contrast, the IC Verification Engineer concentrates on testing and validating the design to catch errors before fabrication.

What are the key skills and qualifications needed to thrive as an IC Physical Design Engineer, and why are they important?

To excel as an IC Physical Design Engineer, you need a solid background in electrical engineering, VLSI design, and familiarity with semiconductor fabrication processes, often supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as experience with timing analysis, floorplanning, and physical verification, is typically required. Strong problem-solving skills, attention to detail, and effective teamwork are important soft skills that help you address design challenges and meet project deadlines. These skills and qualities are crucial for optimizing chip performance, ensuring manufacturability, and delivering successful silicon products.
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What cities are hiring for Ic Physical Design Engineer jobs? Cities with the most Ic Physical Design Engineer job openings:
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Ic Physical Design Engineer jobs near you
Infographic showing various Ic Physical Design Engineer job openings in the United States as of June 2026, with employment types broken down into 100% Full Time. Highlights an 80% In-person, and 20% Hybrid job distribution, with an average salary of $139,408 per year, or $67 per hour.

Physical Design Engineer

RAVIN IT SOLUTIONS, Inc

Mountain View, CA • On-site

$159K - $163K/yr

Other

Posted 6 days ago

Key responsibilities

  • Drive block-level physical design implementation from netlist to GDSII.

  • Perform floor planning, power planning, placement, clock tree synthesis, routing, and physical verification.

  • Optimize designs for Power, Performance, and Area (PPA) targets and achieve timing closure across multiple corners and modes.

Job description

Physical Design Engineer (PD / PnR / PPA / Timing Closure)
Location: Mountain View CA (Onsite)

Job Description
We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities
• Drive block-level physical design implementation from netlist to GDSII.
• Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills
• Strong experience in Physical Design and PnR flow.
• Hands-on expertise in:
o Floor planning
o Placement & Optimization
o Clock Tree Synthesis (CTS)
o Routing
o Timing Closure
o Static Timing Analysis (STA)
o Timing Constraints (SDC)
o EMIR Analysis
o PPA Optimization
• Experience with industry-standard EDA tools such as:
o Synopsys Fusion Compiler / ICC2
o PrimeTime
o Cadence Innovus (optional)
o Red Hawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications
• Bachelor''s or Master''s degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.

Apply