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Ic Package Design Engineer Jobs (NOW HIRING)

Apple

IC Package Design Engineer

Austin, TX · On-site

$134K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA · On-site

$146K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Austin, TX

$175K - $308K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...

Etched

IC Package Engineer

Cupertino, CA · On-site

$2.0K/mo

IC Package Engineer We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

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All JobsIc Package Design Engineer Jobs

Ic Package Design Engineer information

See salary details

$90K

$136.5K

How much do ic package design engineer jobs pay per year?

As of Aug 2, 2026, the average yearly pay for ic package design engineer in the United States is $135,040.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is an IC Package Design Engineer job?

An IC Package Design Engineer is responsible for designing and developing semiconductor chip packaging to ensure electrical, thermal, and mechanical performance. They work with cross-functional teams to optimize package layouts, material selection, and manufacturing processes. Their role involves using CAD tools, simulation software, and collaborating with fabrication and assembly teams to meet product requirements.

What are the key skills and qualifications needed to thrive in the Ic Package Design Engineer position, and why are they important?

Success as an IC Package Design Engineer requires a strong background in electrical engineering, semiconductor packaging principles, and CAD software proficiency, typically supported by a relevant engineering degree. Familiarity with electronic design automation (EDA) tools such as Cadence or Mentor Graphics, and knowledge of industry standards like JEDEC, are highly valuable. Excellent problem-solving, attention to detail, and effective communication skills help navigate complex design challenges and collaborate with cross-functional teams. These abilities are crucial for ensuring robust package designs that meet performance, cost, and manufacturability requirements in the fast-paced semiconductor industry.

What are some common daily responsibilities for an IC Package Design Engineer?

IC Package Design Engineers typically spend their days designing and simulating semiconductor package layouts, reviewing schematics, and ensuring designs meet electrical and thermal requirements. They collaborate closely with PCB designers, test engineers, and manufacturing teams to optimize the package for performance and ease of assembly. Daily work also involves troubleshooting design issues, interacting with vendors for material selection, and participating in design reviews alongside multidisciplinary teams. The role balances hands-on technical tasks with communication, making cross-team coordination a key part of the job.

More about Ic Package Design Engineer jobs
What states have the most Ic Package Design Engineer jobs? States with the most job openings for Ic Package Design Engineer jobs include:
What job categories do people searching Ic Package Design Engineer jobs look for? The top searched job categories for Ic Package Design Engineer jobs are:
Ic Package Design Engineer jobs near you
Infographic showing various Ic Package Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $135,040 per year, or $64.9 per hour.

IC Package Design Engineer with Security Clearance

Zachary Piper Solutions, LLC

San Jose, CA • On-site

$200K - $260K/yr

Other

Medical, Dental, Vision, Retirement, PTO

Re-posted 19 days ago

Job description

Piper Companies is looking for a IC Package Design Engineer to join a cutting-edge start up onsite Monday through Friday near San Jose, CA . The ideal IC Package Design Engineer will lead the physical layout of advanced multi-die substrates that integrate multiple chiplets into a high-density, high-performance package. Responsibilities for the IC Package Design Engineer: * Lead the physical layout of complex multi-die substrates while supporting chiplet-based integration. * Collaborate with package integration, signal/power integrity, and mechanical teams to ensure successful layout implementation. * Drive routing feasibility and co-design alignment with floor planning, mechanical, and system constraints. * Own the full layout process, ensuring performance, manufacturability, and design quality. * Use industry-standard tools like Siemens Xpedition and Cadence Allegro APD to execute and refine substrate designs. Qualifications for the IC Package Design Engineer: * 8+ years of experience in substrate layout design for advanced packaging. * Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance. * Strong background in physical layout and collaboration with ASIC, signal, and power teams. * Proficient in Siemens Xpedition and Cadence Allegro APD * Bachelor's degree in Electrical Engineering preferred. Compensation/Benefits for the IC Package Design Engineer: * Salary Range: $200,000 - $260,000 annually * Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave (if required by law), and Holidays This job opens for applications on 7/14/2026. Applications for this job will be accepted for at least 30 days from the posting date. Keywords: Package Layout, Substrate Design, Multi-Die Integration, Chiplet Packaging, Package Design, Siemens Xpedition, Cadence Allegro APD, Semiconductor Layout, ASIC, packaging technology, Package Design, Package Design Engineer #LI-BR1 #LI-ON SITE

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