ZipRecruiter

Log In

1

Hardware Verification Engineer Jobs in California

QFocus Technologies LLC

Emulation Engineer

Sunnyvale, CA · On-site

$130 - $180/hr

As an HVA Emulation Verification Engineer, you will be at the forefront of pre-silicon validation, ensuring the highest quality and functionality of our hardware before it goes into production.

New

previous page

Showing results 41-60

All JobsHardware Verification Engineer JobsHardware Verification Engineer Jobs in California

Hardware Verification Engineer information

See California salary details

$50.3K

$144.3K

$193.9K

How much do hardware verification engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for hardware verification engineer in California is $144,315.00, according to ZipRecruiter salary data. Most workers in this role earn between $121,900.00 and $160,900.00 per year, depending on experience, location, and employer.

What is a hardware verification engineer?

A Hardware Verification Engineer is responsible for ensuring that semiconductor chips and hardware designs function correctly before manufacturing. They develop and execute testbenches, write verification plans, and use tools like SystemVerilog and UVM to simulate and validate designs. Their job involves debugging issues, writing test cases, and collaborating with design engineers to ensure the final product meets specifications. This role is crucial in preventing costly errors in hardware production and ensuring high reliability in electronic devices.

What does a hardware verification engineer do?

As a Hardware Verification Engineer, your daily responsibilities often include developing and executing test plans, writing verification code using HDLs, running simulations, and analyzing results to identify and resolve design issues. You’ll collaborate closely with design engineers to understand the architecture and specifications, and work with other verification team members to ensure thorough coverage of all test scenarios. The role may also involve documenting findings, participating in design reviews, and using advanced verification methodologies to improve the efficiency and accuracy of test processes. This combination of technical and collaborative work makes the position dynamic and impactful in ensuring high-quality hardware products.

What skills and qualifications are needed to be a hardware verification engineer?

To thrive as a Hardware Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Familiarity with hardware description languages (HDLs) like Verilog or VHDL, simulation tools such as ModelSim, and methodologies like UVM is essential. Strong analytical thinking, attention to detail, and effective communication skills are vital for collaborating with design teams and debugging complex systems. These skills and qualities are crucial to ensure that hardware products meet performance, functionality, and reliability standards before production.

What are the most commonly searched types of Hardware Verification Engineer jobs in California?

The most popular types of Hardware Verification Engineer jobs in California are:

What are popular job titles related to Hardware Verification Engineer jobs in California?

For Hardware Verification Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Hardware Verification Engineer jobs in California look for?

The top searched job categories for Hardware Verification Engineer jobs in California are:

Hardware Verification Engineer jobs near you
Infographic showing various Hardware Verification Engineer job openings in California as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution, with an average salary of $144,315 per year, or $69.4 per hour.

Digital Verification Engineer

NextHop AI

Santa Clara, CA • On-site

$160K - $196K/yr

Full-time

Re-posted yesterday

Job description

Digital Verification Engineer
Location: Santa Clara, CA
Ladder: Silicon / Hardware Design
Travel: Minimal (0-10%)
Role Overview
At Nexthop AI, the correctness of our digital logic is non-negotiable - a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation - long before they reach silicon, a board, or a customer's rack.
Key Responsibilities
1. Verification Environment Ownership
  • Own the testbench: Design, build, and maintain the verification environments for our digital subsystems - from block level through full-chip / subsystem integration - for both FPGA and ASIC targets.
  • Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.
  • Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.

2. Test Development & Coverage
  • Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.
  • Coverage-driven closure: Define functional and code-coverage goals and drive them to closure - identifying coverage holes and writing the stimulus to fill them.
  • Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.

3. Simulation, Debug & Regression
  • Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.
  • Regression: Stand up and maintain automated regression suites - keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.
  • Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design-debug loop.

4. System Bring-up & HW/SW Co-validation
  • Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.
  • Software collaboration: Partner with firmware / software engineers during system bring-up - validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.
  • Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.

Required Qualifications
  • Experience: 3-7 years of digital verification experience on FPGA or ASIC designs.
  • Language: Proficiency in Verilog (SystemVerilog strongly preferred).
  • Tools: Hands-on experience with logic simulators - Modelsim / Questasim and/or NC-Verilog.
  • Methodology: Solid grounding in logic-simulation and verification fundamentals - testbench construction, constrained-random stimulus, functional / code coverage, and assertions.
  • Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.

Strong Pluses
  • Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).
  • Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.
  • Structured verification methodology experience (UVM or equivalent).
  • Familiarity with networking / switching datapaths or high-speed interfaces.

What Success Looks Like
  • Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.
  • Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage - no block signs off on "it seems to work."
  • A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it's introduced, so designers refactor with confidence.
  • Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly - no late-stage firefighting.

Apply