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Google Asic Design Engineer Jobs in Georgia (NOW HIRING)

Falcomm

ASIC Engineer

Atlanta, GA · On-site

$159K/yr

Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout ... Work with verification engineers to define testbenches and ensure robust design validation

Falcomm

ASIC Engineer

Atlanta, GA

$159K/yr

Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout ... Work with verification engineers to define testbenches and ensure robust design validation

Falcomm

ASIC Engineer

Atlanta, GA · On-site

$159K/yr

Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout ... Work with verification engineers to define testbenches and ensure robust design validation

Kanak Elite Services Inc

UI/UX Design Engineer

Atlanta, GA · On-site

$90K - $112K/yr

Position : UI/UX Design Engineer Location : Atlanta GA Hybrid (Must be local) Duration : long term ... Knowledge of analytics tools (Google Analytics, Tag Manager, Data Studio). * Understanding of SEO ...

Google

Manufacturing Test Engineer

Atlanta, GA · On-site

Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. As a Manufacturing Test Engineer ...

campus4tech

UI/UX Design Engineer

Atlanta, GA · On-site

$90K - $112K/yr

Job Title: UI/UX Design Engineer Job Type: C ontract - Hybrid Duration: 6 months (possibility of ... tools (Google Analytics, Tag Manager, Data Studio). • Understanding of SEO principles and ...

nLeague Services Inc

UI/UX Design Engineer

Atlanta, GA · On-site

$90K - $112K/yr

DECAL UI/UX Design Engineer (786569) Client: GA DECAL(Georgia Department of Early Care and Learning ... Knowledge of analytics tools (Google Analytics, Tag Manager, Data Studio). * Understanding of SEO ...

Avnet, Inc.

Field Application Engineer

Atlanta, GA

Develop relationships with and become trusted advisor to (system) engineers & architects in your ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...

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Google Asic Design Engineer information

See Georgia salary details

$79.4K

$126.8K

$170.6K

How much do google asic design engineer jobs pay per year?

As of Aug 27, 2026, the average yearly pay for google asic design engineer in Georgia is $126,822.00, according to ZipRecruiter salary data. Most workers in this role earn between $111,000.00 and $152,000.00 per year, depending on experience, location, and employer.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

Are Google ASIC Design Engineers in demand?

ASIC Design Engineers at Google are in high demand due to the growing need for specialized hardware acceleration and efficient chip designs in data centers and AI applications. Skills in digital design, verification, and hardware description languages like Verilog or VHDL are highly valued, and the role often requires experience with EDA tools and FPGA prototyping. The demand is expected to remain strong as companies continue to develop custom chips for performance and energy efficiency.

How much does a Google ASIC Design Engineer make?

A Google ASIC Design Engineer typically earns a base salary ranging from $120,000 to $200,000 annually, with total compensation often including bonuses and stock options. Compensation varies based on experience, location, and level within the company, and the role requires expertise in hardware design, verification, and EDA tools.

What is the salary of Google ASIC Design Engineer in Google?

The salary for a Google ASIC Design Engineer typically ranges from $120,000 to $200,000 annually, depending on experience, location, and level within the company. Compensation may also include bonuses, stock options, and benefits, reflecting industry standards for specialized hardware design roles at major tech companies.

What are popular job titles related to Google Asic Design Engineer jobs in Georgia?

For Google Asic Design Engineer jobs in Georgia, the most frequently searched job titles are:

What job categories do people searching Google Asic Design Engineer jobs in Georgia look for?

The top searched job categories for Google Asic Design Engineer jobs in Georgia are:

What cities in Georgia are hiring for Google Asic Design Engineer jobs?

Cities in Georgia with the most Google Asic Design Engineer job openings:

Google Asic Design Engineer jobs near you
Infographic showing various Google Asic Design Engineer job openings in Georgia as of August 2026, with employment types broken down into 6% As Needed, 72% Full Time, and 22% Contract. Highlights an 94% In-person, and 6% Remote job distribution, with an average salary of $126,822 per year, or $61 per hour.

ASIC Engineer

Falcomm

Atlanta, GA • On-site

$159K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 16 days ago

Job description

Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power amplifier and wireless solutions. Our mission is to push the boundaries of performance, efficiency, and integration in modern communication systems.

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital integrated circuits that interface with our RF technologies. This role will contribute to the design, implementation, and verification of ASIC components within larger system-on-chip platforms. The position requires strong collaboration with RFIC, analog, verification, and system engineering teams to deliver high-performance silicon solutions.

Responsibilities:
  • Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout
  • Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area
  • Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures.
  • Perform synthesis, timing closure, and power optimization
  • Work with verification engineers to define testbenches and ensure robust design validation
  • Support functional verification and debugging of ASIC components in collaboration with verification teams.
  • Assist with synthesis, timing analysis, and physical implementation activities to ensure design readiness for tape-out.
  • Contribute to silicon bring-up, debugging, and post-silicon validation activities.
  • Document design architecture, implementation details, and verification results.

Requirements

  • Bachelor’s or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
  • 1-3 years of experience developing and implementing in ASIC design.
  • Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
  • Solid understanding of digital design fundamentals (timing, clocking, power, etc.)
  • Experience with ASIC tool flows (e.g., Synopsys, Cadence, or similar)
  • Familiarity with verification methodologies (UVM is a plus)
  • Strong problem-solving skills and ability to work across disciplines
  • Must be willing to work full-time, onsite, in Atlanta, GA.
Preferred Skills
  • Strong problem-solving skills in complex digital design areas such as clock domain crossing, timing optimization, and low-power design techniques.
  • Hands-on experience with industry EDA tools including HDL simulators, linting tools, and FPGA development platforms.
  • Proficiency in scripting languages such as Python or TCL to support design automation and verification workflows.

Benefits

  • Competitive Salary and Equity Package
  • Comprehensive Health, Dental, and Vision Insurance
  • 401(k) Retirement Plan
  • Paid Time Off (PTO) and Sick Leave

Disclosure:

  • Falcomm is an Equal Opportunity Employer; employment with Falcomm is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
  • Applicants wishing to view a copy of Falcomm’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify Falcomm.
  • To conform to U.S. Government export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

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